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BOOKS

• Hardware Design - Formaler Entwurf Digitaler Schaltungen
  Jörg Keller, Wolfgang Paul, 1995

• The Complexity of Simple Computer Architectures
  Silvia M. Müller, Wolfgang Paul, 1995

• Computer Architecture: Complexity and Correctness
  Silvia M. Müller, Wolfgang Paul, Further excerpts available upon request. 2000

PAPERS

• Mirroring: A Technique for Pipelining of Semi-Systolic and Systolic Arrays
  Michael Braun, Guy Even, T. Walle, 1997

• On the Correctness of Hardware Scheduling Mechanisms for Out-Of-Order Execution
  Silvia M. Müller, Wolfgang Paul, 1998

• Complexity and Correctness of Computer Architectures
  Silvia M. Müller, 1997

• Making the Original Scoreboard Mechanism Deadlock Free
  Silvia M. Müller, Wolfgang Paul, 1996

• Parallelisierung aller APL-Operationen
  Wolfgang Paul, J. Sauermann, 1996

• Building the 4 Processor SB-PRAM Prototype
  Peter Bach, Michael Braun, Arno Formella, Jörg Friedrich, Thomas Gruen, Cedric Lichtenau, 1997

• A Dual Mode IEEE Multiplier
  Guy Even, Silvia M. Müller, Peter Michael Seidel, 1997

• On the design of IEEE compliant floating point units
  Guy Even, Wolfgang Paul, 1997

• Conflict-Free Access to Multiple Single-Ported Register Files
  Silvia M. Müller, U. Vishkin, 1997

• A Hardware Scheduler for Controlling Variable Latency Functional Units
  Silvia M. Müller, 1999

• On the Scheduling of Variable Latency Functional Units.
  Silvia M. Müller, 1999

• The Impact of Hardware Scheduling Mechanisms on the Performance and Cost of Processor Designs
  Silvia M. Müller, Holger Leister, Peter Dell, Nikolaus Gerteis, Daniel Kröning, 1999

• A Rigorous Correctness Proof of the Tomasulo Scheduling Algorithm with Precise Interrupts
  Daniel Kröning, Silvia M. Müller, Wolfgang Paul, 1999

• Proving the Correctness of Processors with Delayed Branch using Delayed PC
  Silvia M. Müller, Wolfgang Paul, Daniel Kröning, 2000

• The Impact of Write-Back on the Cache Performance
  Silvia M. Müller, Daniel Kröning, 2000

• The DATIS-P Parallel Machine
  Wolfgang Paul, Dieter Scheerer, 1991

• Cost Effectiveness of Data Flow Machines and Vector Processors
  Arno Formella, Werner Massonne, Wolfgang Paul, 1992

• Proving the Correctness of Pipelined Micro-Architectures
  Daniel Kröning, Wolfgang Paul, Silvia M. Müller, 2000

• Proving the Correctness of a Complete Microprocessor
  Christian Jacobi, Daniel Kröning, 2000

• Highly Concurrent Locking in Shared Memory Database Systems
  Christian Jacobi, Cedric Lichtenau, 1999

• Formal Verification of a Basic Circuits Library
  Christoph Berg, Christian Jacobi, Daniel Kröning, 2001

• Automated Pipeline Design
  Daniel Kröning, Wolfgang Paul, 2001

• On the Complexity of Booth Recoding
  Wolfgang Paul, Peter Michael Seidel, 1998

• High-Speed Redundant Reciprocal Approximation
  Peter Michael Seidel, 1998

• How Many Logic Levels Does Floating-point Addition Require?
  Peter Michael Seidel, Guy Even, 1998

• How to half the latency of IEEE compliant floating-point multiplication.
  Peter Michael Seidel, 1998

• A comparison of three different rounding algorithms for floating-point multiplication
  Guy Even, Peter Michael Seidel, 1999

• High-Speed Redundant Reciprocal Approximation
  Peter Michael Seidel, 1999

• A comparison of three different rounding algorithms for floating-point multiplication
  Guy Even, Peter Michael Seidel, 2000

• A dual mode IEEE multiplier
  Guy Even, Silvia M. Müller, Peter Michael Seidel, 2000

• Formal Verification of the VAMP Floating Point Unit
  Christoph Berg, Christian Jacobi, 2001

• Formal Verification of a Theory of IEEE Rounding
  Christian Jacobi, 2001

• Formal Verification of the VAMP Microprocessor (Project Status)
  Christoph Berg, Sven Beyer, Christian Jacobi, Daniel Kröning, Dirk Leinenbach, 2002

Master/Phd Thesis

• The influence of the communication startup time on the performance of multicomputers, running numerical applications
  Silvia M. Müller, 1989

• RISC and CISC: Optimization and Comparison of Architectures
  Silvia M. Müller, 1991

• On the Realization of the PRAM Model (German)
  Jörg Keller, 1992

• Performance and Quality of Vectorcomputers for Numerical Applications (German)
  Arno Formella, 1992

• Performance and Optimization of CPU architectures with VAX and IBM/370 instruction sets
  Dietmar Schmidt, 1992

• Performance and Cost Effectiveness of Data Flow Architectures (German)
  Werner Massonne, 1994

• Quantitative Analysis of Pipelined DLX Architectures
  Robert Knuth, 1996

• Quantitative Analysis of Precise Interrupt Mechanisms for Processors with Out-Of-Order Execution
  Holger Leister, 1999

• Quantitative Analysis of I/O architectures (German)
  Thomas Gruen, 1994

• The Performance Impact of Precise Interrupt Handling on a RISC Processor (German)
  Nikolaus Gerteis, 1998

• The Performance Impact of the Standard Mechanisms for Out-of-Order Dispatch on a RISC Processor (German)
  Peter Dell, 1998

• The Impact of Fanout on the Cost and Performance of a DLX Fixed-Point Core
  Dierk Jordan, 1998

• Hardware support for Virtual Memory
  Daniel Wannemacher, 1999

• Design and Evaluation of a RISC Processor with a Tomasulo Scheduler
  Daniel Kröning, Master's Thesis 1999

• Design and Evaluation of a Superscalar RISC Processor
  Mark Hillebrand, 2000

• A Relational Database System for the SB-PRAM; Concurrency Control and TPC-B (in german)
  Christian Jacobi, 1999

• On the Design of IEEE Compliant Floating-Point Units and their Quantitative Analysis.
  Peter Michael Seidel, 1999

Other

• Cache Simulations for a 32-bit RISC Prozessor on a SPEC Workload
  Daniel Kröning, Lab Project Documentation 1997

• Run Time Simulation of a DLX Processor with Stall Engine
  Peter Dell, Lab Project Documentation 1997

• Proving the Correctness of a Complete Floating Point Unit on the Gate Level
  Christian Jacobi, Talk given at the AOC Workshop on Certified Arithmetic at ENS Lyon 2000

• Comparing the SB-PRAM with a perfect PRAM using Quicksort
  Christian Jacobi, Jochen Roehrig, Unpublished