Computer Architecture

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Formal Verification
Formal Verification of Hardware Systems
Hardware Scheduling Algorithms, Performance and Correctness of Schedulers
Floating Point Units
Design and Evaluation of IEEE Compliant Floating Point Units
Processors and Systems
Entire Processors, Vector and Dataflow Architectures, Parallel Machines
Memory Design
Caches, Register Files, Virtual Memory, I/O Architectures
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Last modified on Sep 25, 2000 by Daniel Kröning.