PAPERS

• The Impact of Hardware Scheduling Mechanisms on the Performance and Cost of Processor Designs
  Silvia M. Müller, Holger Leister, Peter Dell, Nikolaus Gerteis, Daniel Kröning, 1999

• A Rigorous Correctness Proof of the Tomasulo Scheduling Algorithm with Precise Interrupts
  Daniel Kröning, Silvia M. Müller, Wolfgang Paul, 1999

• Proving the Correctness of Processors with Delayed Branch using Delayed PC
  Silvia M. Müller, Wolfgang Paul, Daniel Kröning, 2000

• The Impact of Write-Back on the Cache Performance
  Silvia M. Müller, Daniel Kröning, 2000

• Proving the Correctness of Pipelined Micro-Architectures
  Daniel Kröning, Wolfgang Paul, Silvia M. Müller, 2000

• Proving the Correctness of a Complete Microprocessor
  Christian Jacobi, Daniel Kröning, 2000

• Formal Verification of a Basic Circuits Library
  Christoph Berg, Christian Jacobi, Daniel Kröning, 2001

• Automated Pipeline Design
  Daniel Kröning, Wolfgang Paul, 2001

• Formal Verification of the VAMP Microprocessor (Project Status)
  Christoph Berg, Sven Beyer, Christian Jacobi, Daniel Kröning, Dirk Leinenbach, 2002

Master/Phd Thesis

• Design and Evaluation of a RISC Processor with a Tomasulo Scheduler
  Daniel Kröning, Master's Thesis 1999

Other

• Cache Simulations for a 32-bit RISC Prozessor on a SPEC Workload
  Daniel Kröning, Lab Project Documentation 1997