Publikationen / Publications

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Books

[B1]

with W. J. Paul. The Complexity of Simple Computer Architectures. Lecture Notes in Computer Science 995, Springer Verlag, October 1995.

[B2]

with W. J. Paul. Complexity and Correctness of Computer Architectures. to appear by Springer. Topics: pipelining, interrupt handling, memory system design, and IEEE compliant floating-point units. Further excerpts available upon request.

Journal Papers (refereed)

[J1]

with H. Eissfeller. A Note on Reducing the Communication Costs in Explicit Time Stepping Methods on Parallel Computers. Applied Mathematics and Computation, 39(3):191-197, 1991. (short version of [C3])

[J2]

with D. Scheerer. A Method to Parallelize Tridiagonal Solvers. Parallel Computing, 17:181-188, 1991. (extended version of [C2])

[J3]

with W. J. Paul. On the Correctness of Hardware Scheduling Mechanisms for Out-Of-Order Execution. Journal of Circuits, Systems and Computers, 8(2):301-314, 1998, World Scientific Publishers.

[J4]

with G. Even, P-M. Seidel. A Dual Precision IEEE Floating-Point Multiplier. Submitted to INTEGRATION, the VLSI journal, February 1999. (extended version of [C11]).

Conference Papers and Book Chapters

[C1]

with W. J. Paul (invited). Contributions of Theoretical Computer Science, Applied Computer Science and Numerical Mathematics to the Design of Parallel Computers. Proc. 11th World Computer Congress, Information Processing (IFIP), Vol. 11, p. 459-460. Elsevier Science Publishers, 1989.

[C2]

A Method to Parallelize Tridiagonal Solvers, Proc. 5th Distributed Memory Computing Conference (DMCC-5), Vol. I, p. 340-345. IEEE Computer Society Press, 1990. (short version of [J2])

[C3]

with H. Eissfeller. The Triangle Method for Saving Startup Time in Parallel Computers. Proc. 5th Distributed Memory Computing Conference (DMCC-5), Vol. I, p. 568-571. IEEE Computer Society Press, 1990. (also available as [J1])

[C4]

with W. J. Paul (invited). Towards a Formal Theory of Computer Architecture. Proc. PARCELLA 90: Research in Informatics, Vol. 2, p. 157-169. Akademie-Verlag, 1990.

[C5]

with A. Bingert, A. Formella, W. J. Paul. Isolating the Reasons for the Performance of Parallel Machines on Numerical Programs. In C. Kessler (Ed.), Automatic Parallelization, p. 45-77, Vieweg Advanced Studies in Computer Science, Vieweg Publishers, 1994.

[C6]

with A. Bingert, A. Formella, W. J. Paul. Isolating the Reasons for the Performance of Parallel Machines on Numerical Programs II. In T. Hey and J. Ferrante (Ed.), Portability and Performance for Parallel Processing, p. 223-269, Wiley & Sons, Ltd, 1994.

[C7]

with B. Gomes. Efficient Mapping of Randomly Sparse Neural Networks on Parallel Vector Supercomputers. Proc. 6th IEEE Symposium on Parallel and Distributed Processing (SPDP), p. 170-177, IEEE Computer Society Press, 1994.

[C8]

Complexity and Correctness of Computer Architectures, Proc. 4th Workshop on Parallel Systems and Algorithms (PASA'96), p. 125-146, World Scientific Publishing Co., 1997, (invited). COMMENT

[C9]

with W. J. Paul. Making the Original Scoreboard Mechanism Deadlock Free. Proc. 4th Israel Symposium on Theory of Computing and Systems (ISTCS), p. 92-99, IEEE Computer Society Press, 1996. COMMENT

[C10]

with U. Vishkin. Conflict-Free Access to Multiple Single-Ported Register Files. Proc. 11th International Parallel Processing Symposium (IPPS'97), p. 672-678, IEEE Computer Society Press, 1997.

[C11]

with G. Even, P-M. Seidel. A Dual Mode IEEE Floating-Point Multiplier. Proc. 2nd IEEE International Conference on Innovative Systems in Silicon (ISIS'97), p. 282-289, IEEE Computer Society Press, October 1997.

[C12]

A Hardware Scheduler for Controlling Variable Latency Functional Units. Proc. 17th IASTED International Conference on Applied Informatics (AI'99), p. 581-583, ACTA Press, 1999.

[C13]

On the Scheduling of Variable Latency Functional Units. Proc. 11th ACM Symposium on Parallel Algorithms and Architectures SPAA'99, p. 148-154, ACM Press, 1999. ACM copyright

[C14]

with H.W. Leister, P. Dell, N. Gerteis, D. Kroening. The Impact of Hardware Scheduling Mechanisms on the Performance and Cost of Processor Designs. Proc. 15th GI/ITG Conference `Architektur von Rechensystemen' ARCS'99, p. 65-73, VDE Verlag. (Copyrights VDE-Verlag GMBH)

[C15]

with D. Kroening, W.J. Paul. A Rigorous Correctness Proof of a Tomasulo Scheduler Supporting Precise Interrupts. Proc. SCI'99/ISAS'99 International Conference.

[C16]

with W.J. Paul, D. Kroening. Proving the Correctness of Processors with Delayed Branch using Delayed PCs. In I. Althoefer et al. (Ed); Numbers, Information and Complexity; Kluwer, 1999. To appear in Proc. IEEE International High Level Design Validation and Test Workshop HLDVT'99, 1999.

[C17]

with W.J. Paul. The Decomposition Theorem for IEEE Floating Point Rounding.

[C18]

with D. Kroening. The Impact of Write-Back on the Cache Performance. Submitted to 18th IASTED International Conference on Applied Informatics (AI'2000)

Thesis

[E1]

Die Auswirkung der Startup-Zeit auf die Leistung paralleler Rechner bei numerischen Anwendungen. (tr.: The influence of the communication startup time on the performance of multicomputers, running numerical applications). Master's Thesis, University of Saarland, Mathematics Department, Saarbruecken, 1989.

[E2]

RISC und CISC: Optimierung und Vergleich von Architekturen, (tr.: RISC and CISC: Optimization and Comparison of Architectures). PhD Thesis, University of Saarland, Computer Science Department, Saarbruecken, 1991.

Reports

[R1]

with P. Bergmann, J. Keller, T. Malter, W. J. Paul, T. Pöschel, O. Schlüter, L. Thiele. Implementierung eines informationstheoretischen Ansatzes zur Bilderkennung. (tr.: Implementation of an information theoretical approach to computer vision). Proc. I.I.I.-Forum Saarbruecken, (Innovative Information Infrastructures), p. 187-197. Springer, 1988.

[R2]

A Performance Analysis of the CNS-1 on Large, Dense Backpropagation Networks. Technical Report TR-93-046, ICSI, Berkeley, 1993.

[R3]

All-to-all Broadcast on the CNS-1. Technical Report TR-93-082, ICSI, Berkeley, 1993.

[R4]

with B. Gomes. A Performance Analysis of CNS-1 on Sparse Connectionist Networks. Technical Report TR-94-009, ICSI, Berkeley, 1994.

[R5]

with W. J. Paul. A Formal Model for Pre-Hardware Cost/Time Trade-off Analyses and Selected Results. ACM Workshop on Pre-Hardware Performance Analysis, Santa Margherita, June 1995.

[R6]

with R. Knuth. Correctness of a Mechanism for Precise Nested Processing of Interrupts in Pipelined Designs, TR 1996.

Talks at Workshops without Proceedings

09/98

with H. Leister, P. Dell, N. Gerteis, K. Kroening. The Impact of Hardware Scheduling Mechanisms on the Performance and Cost of Processor Designs. Dagstuhl Seminar: Architectural and Arithmetic Support for Multimedia, IBFI, Schloss Dagstuhl, Germany. (available as [C14])

09/98

A Hardware Scheduler for Controlling Variable Latency Functional Units. Dagstuhl Seminar: Architectural and Arithmetic Support for Multimedia, IBFI, Schloss Dagstuhl, Germany. (available as [C12])

06/95

A Formal Model for Pre-Hardware Cost/Time Trade-off Analyses and Selected Results. 1st ACM Workshop: Pre-Hardware Performance Analysis Techniques (22nd ISCA), Santa Margherita, Italy. (available as [R5])

09/89

The Influence of the Startup Time on the Performance of Multicomputers running Numerical Applications. Workshop on Efficient Algorithms, Oberwolfach, Germany.