| ALU ( lecture of 21.10.2004 ) |
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| Instruction Set Architecture (ISA) (modified on 01.12.2004) |
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| Ph.D. Th. D.Kroening. Chapter 4: Pipelined Machines |
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| Cache Accesses |
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| Iakov Dalinger, Mark Hillebrand, and Wolfgang J. Paul. On the Verification of Memory Management Mechanisms. Technical Report, 2005. |
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| Addition to the lecture of 01.02.05 (Memory Managment) |
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| D. Kroening, S. Mueller, W. Paul, "A Rigorous Correctness Proof of a Tomasulo Scheduler Supporting Precise Interrupts" |
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| Ph.D. Th. D.Kroening. Chapter 6: Out Of Oder Execution |
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