Institute for Computer Architecture
and Parallel Computing
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Project overview
In this project, we investigate the maximum pipeline depth of a processor. This entails both design and correctness of special stall- and forwarding-circuits as well as pipelined RAM-accesses. Additionally, we determine the optimum pipeline depth with respect to benchmarks.
Project status
The design of a parameterized super-pipelined processor with 5 combinational gate delays per register stage ist finshed on paper. The correctness of the stall- and forwarding-circuits as well as the pipelined RAM has been shown mathematically. We currently want to develop a simulator in order to determine the optimum pipeline depth.
Project members
Dr. Jochen M. PreiƟ