Institut für Rechnerarchitektur
und Parallelrechner
Peter Böhm
Universität des Saarlandes   Gebäude E1 3
FR 6.2 Informatik   Raum 325
Postfach 151150   Tel: +49 (0)681 302-64715
D-66041 Saarbrücken   Fax: +49 (0)681 302-4290
Germany   eMail:
Alkassar, Eyad and Böhm, Peter and Knapp, Steffen   EE BibTeX
Formal Correctness of a Gate-Level Automotive Bus Controller Implementation.
In Bernd Kleinjohann and Lisa Kleinjohann and Wayne Wolf, editors, 6th IFIP Working Conference on Distributed and Parallel Embedded Systems (DIPES08),
pages 57-68, Springer, 2008.
Alkassar, Eyad and Böhm, Peter and Knapp, Steffen   EE BibTeX
Correctness of a Fault-Tolerant Real-Time Scheduler Algorithm and its Hardware Implementation.
In Formal Methods and Models for Codesign (MEMOCODE'2008),
pages 175--186, IEEE Computer Society Press, 2008.
Beyer, S. and Böhm, P. and Gerke, M. and Hillebrand, M. and In der Rieden, T. and Knapp, S. and Leinenbach, D. and Paul, W.J.   EE BibTeX
Towards the Formal Verification of Lower System Layers in Automotive Systems.
In 23nd IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD 2005), 2-5 October 2005, San Jose, CA, USA, Proceedings,
pages 317-324, IEEE, 2005.
ISBN 0-7695-2451-6