Institut für Rechnerarchitektur und Parallelrechner

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Dr. Jonas Oberhauser

Universität des Saarlandes		Gebäude E1 3
FR 6.2 Informatik		Raum 306
Postfach 151150		Tel: +49 (0)681 302-4130
D-66041 Saarbrücken		Fax: +49 (0)681 302-4290
Germany		eMail: jonas@wjpserver.cs.uni-saarland.de

Lebenslauf

1991		Birth
2010 - 2012		Bachelor, Thesis in Computational Logic
2012 - 2014		Master Equivalent, Research Labs in Computational Logic and Pipelined Processor Correctness
2014 - 2016		PhD, Thesis in Justification of High-Level Language Semantics for Multicore OS

Forschungsinteressen

Low-level Concurrency

Hardware Correctness and Optimization

Operating System Correctness and Optimization

Weak Memory

Computational Logic

Realistic Language Semantics

Efficient and Low-Effort Reasoning over Concurrent Programs

Private Homepage

Publikationen

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Oberhauser, Jonas			BibTeX
Order Reduction for Interruptible Multi-Core Operating Systems.
In Chechik, M. and Blazy, S., editors, 8th International Conference on Verified Software: Theories, Tools, and Experiments (VSTTE'16),
Toronto, Canada
2016.

Paul, W.J. and Baumann, C. and Lutsyk, P. and Schmaltz, S. and Oberhauser, J.			BibTeX
System Architecture as an Ordinary Engineering Discipline.
Springer, 2016.

Paul, W.J. and Lutsyk, P. and Oberhauser, J.			BibTeX
Multi-core System Architecture.

Lecture notes, Saarland University, 2016.

Oberhauser, Jonas			BibTeX
A Simpler Reduction Theorem for x86-TSO.
In Gurfinkel, A. and Seshia, S. A., editors, 7th International Conference on Verified Software: Theories, Tools, and Experiments (VSTTE'15),
San Francisco, CA, USA
2015.