Computer Architecture 2 |
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In this class we treat three subjects 1) Floating-Point Units: We formalize the IEEE floating point standard and develop an appropriate theory of rounding. Then we proceed to construct a dual precision floating point unit and prove that it is fully compatible with the IEEE standard. 2) Interfaces for Real Time Busses: We define the protocol of a real time bus similar to the FlexRay bus used in the German automotive industry. Because different control units on such a bus have oszillators with almost but not completely equal frequency the construction of interfaces for such busses is far from trivial. In particular one has to construct serial interfaces for the transmission of messages across clock domains, one has to implement clock synchronisation for the timers in different interfaces and one has to show the absence of bus contention on the bus, that is shared by interfaces from different clock domains. 3) Pipelined Multi-Processors: We extend the pipelined MIPS processor from Computer Architecture I with a store buffer, a memory-management unit, and an interrupt mechanism. If time is left we will integrate several pipelined processors with the shared memory construction, obtaining a pipelined multi-processor implementation. Prerequisites: Being familiar with the content of last semester's computer architecture I lecture is clearly helpful but not strictly necessary. |
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