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Within this practical core lecture, we will deal with the specification, implementation, correctness, and evaluation of computer hardware.
The following topics will be covered:
  • Basics: combinational & clocked circuits
  • MIPS instruction set architecture
  • MIPS implementation: sequential, pipelined implementation, improved pipelined implementation (forwarding, branch prediction)
  • Caches and memory: direct mapped caches, associative caches, single-port RAM, multi-port RAM
  • Caches and shared memory for multicore systems: MOESI protocol specification, implementation, and correctness proof
  • Multi-core MIPS processor: specification, implementation and correctness
  • Virtual memory support
Organizational stuff
  • Tutorials: Monday, 16:00 - 18:00 (Group A, E13 016) and Thursday, 14:00 - 16:00 (Group B, E13 107)
  • Please, register for the course in the registration section.
  • Scheduled exam dates:
    February 12, 2015, 12:00 in E13 HS001 (exam)
    March 31, 2015, 14:00 in E13 HS001 (re-exam)
  • Exam Prerequisites:
    In order to be admitted to the oral exam you have to achieve 50% of all exercise points.
    In addition each student has to present at least two exercise solutions.
  • Please, register for the exam in HISPOS
  • Office hours of the teaching assistant: Friday 16:00-18:00 (building E1.3, room 306).
Tutorials start on Monday, Nov 10 (Group A) / Thursday, Nov 13 (Group B)
Exam time and room changed
Errata of the main textbook is now available
Re-exam time and room changed