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A Pipelined Multi Core MIPS Machine: Hardware Implementation and Correctness Proof (ver. from 17.04.12) |
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A Pipelined Multi Core MIPS Machine: Hardware Implementation and Correctness Proof (ver. from 14.02.13) |
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- [2]
- Müller, S.M. and Paul, W.J.
Computer Architecture, Complexity and Correctness
Springer Verlag ISBN 3-540-67481-0
Please also take a look at the errata list for known bugs.
- [2]
- Mark A. Hillebrand,
Lecture Notes of lecture Computer Architecture from WS06/07
- [3]
- Paul Sweazey, Alan Jay Smith:
A class of compatible cache consistency protocols and their support by the IEEE futurebus., ACM New York, NY, USA , 1986
- [4]
- Kröning, Daniel: Formal
Verification of Pipelined Microprocessors., PhD thesis, Saarland University, Saarbrücken, 2001
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