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Within this practical core lecture, we will deal with the specification, implementation, correctness, and evaluation of computer hardware.

The following topics will be covered:
- Basics: Combinational & Clocked circuits
- DLX instruction set architecture
- DLX implementation: Sequential, Pipelined implementation, Improved pipelined implementation (forwarding, branch prediction)
- Memory system with caches: In order to gain fast memory accesses, a memory system with caches will be presented.
- Virtual memory support: A virtual memory support is essential for multitasking operating systems; topics like memory management units are covered.
- I/O Device support
A support for I/O devices is essential for user interaction, networking, or data storage.

 
Organizational stuff
  • Course starts on Monday, 11.04.2011.
  • Please, register for the course in the registration section.
  • Office hours of the teaching assistant: Thursday 16:00-18:00 (building E1.3, room 319).
  • Tutorials:
    • Group 1(Yash Raj Shrestha) - Tuesday 16:00-18:00 (Room: Seminar Raum 001, Cluster of Excellence),
    • Group 2(Andrey Shadrin) - Friday 14:00-16:00 (Room: Seminar Raum 001, Cluster of Excellence)
    • First Tutorial: Tuesday, 26.04.11
    • Tutorials on May 10th, May 19th, May 27th and July 15th will be held in Room 328, E1.3
News
  • Course starts on Monday, 11.04.2011.
  • Please, register for the course in the registration section.
  • Oral exam: 25.07.11, 09:00 Room: 328, E 1.3
  • Oral re-exam: 30.08.11, 09:00 Room: 328, E 1.3
  • Tutorial on Friday, June 10th is cancelled.
 
Lecture evaluation
Auswertungsinformation Informatik - Evaluation SoSe 2011  
Evaluation SoSe 2011 - Computer Architecture I