Bibliography
 
 
[1]
Müller, S.M. and Paul, W.J. Computer Architecture, Complexity and Correctness Springer Verlag ISBN 3-540-67481-0
Please also take a look at the errata list for known bugs.
[2]
Mark A. Hillebrand, Lecture Notes of lecture Computer Architecture from WS06/07
[3]
Wolfgang Paul, Norbert Schirmer and Ulan Degenbaev. Theory of Memory Saarland University, 2008 PPT
[4]
Paul Sweazey, Alan Jay Smith: A class of compatible cache consistency protocols and their support by the IEEE futurebus., ACM New York, NY, USA , 1986
[5]
Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3A: System Programming Guide PDF
[6]
Kröning, Daniel: Formal Verification of Pipelined Microprocessors., PhD thesis, Saarland University, Saarbrücken, 2001