| Date |
Topic |
Student |
| 10th 10.00 - 11.30 |
Verification of Synchronous Circuits by Symbolic Logic Simulation |
Martin Schaef |
| 14th 10.00 - 11.30 |
Verification of Out-of-Order Processor Desings Using |
Alexandra Tsyban |
|
Complition Function with Reference File |
|
| 15th 10.00 - 11.30 |
Algebraic Models of Correctness for Microprocessors |
Gennady Shmonin |
| 15th 11.45 - 13.15 |
Specification and Verification of ARM6 Microprocessor in HOL |
Oleg Parshin |
| 16th 10.00 - 11.30 | Top-level Refinement in Processor Verification | Ivelina Stavreva |
| 28th 10.00 - 11.30 |
Validity Checking For Combinations of Theories with Equality |
Vasily Tsyba |
