`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   10:08:02 09/18/2007
// Design Name:   DcmClk_unit
// Module Name:   DcmClk_unit_tb.v
// Project Name:  DLX
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: DcmClk_unit
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module DcmClk_unit_tb_v;

	// Inputs
	reg clk_i;
	reg reset_i;

	// Outputs
	wire clk_o;
	wire uartclk_o;
	wire reset_o;

	// Instantiate the Unit Under Test (UUT)
	DcmClk_unit uut (
		.clk_i(clk_i), 
		.reset_i(reset_i), 
		.clk_o(clk_o), 
		.uartclk_o(uartclk_o), 
		.reset_o(reset_o)
	);

	initial begin
		// Initialize Inputs
		clk_i = 0;
		reset_i = 1;

		// Wait 100 ns for global reset to finish
		#100;
		
		reset_i = 0;
        
		// Add stimulus here

	end
      
	always #7.57575 clk_i = !clk_i;
		
endmodule

