`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    18:03:22 07/11/2007 
// Design Name: 
// Module Name:    clk_unit 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module ClkUnit
	(
	     SysClk,   // System Clock
		  EnableRx, // Control signal for receiver
        EnableTx, // Control signal for transmitter
        Reset     // Reset input
	);
	
	input  SysClk;
   output EnableRx;
   output EnableTx;
	input  Reset;


	parameter ClkFrequency = 66000000;
	parameter Baud = 9600;

	// Baud generator for the receiver (we use 16 times oversampling)
	parameter Baud16 = Baud*16;
	parameter Baud16GeneratorAccWidth = 16;
	wire [Baud16GeneratorAccWidth:0] Baud16GeneratorInc = ((Baud16<<(Baud16GeneratorAccWidth-7))+(ClkFrequency>>8))/(ClkFrequency>>7);
	reg [Baud16GeneratorAccWidth:0] Baud16GeneratorAcc;
	always @(posedge SysClk) Baud16GeneratorAcc <= Baud16GeneratorAcc[Baud16GeneratorAccWidth-1:0] + Baud16GeneratorInc;
	wire Baud16Tick = Baud16GeneratorAcc[Baud16GeneratorAccWidth];
	
	assign EnableRx = Baud16Tick;
	
	// Baud generator for the transmitter
	parameter BaudGeneratorAccWidth = 16;
	reg [BaudGeneratorAccWidth:0] BaudGeneratorAcc;
	wire [BaudGeneratorAccWidth:0] BaudGeneratorInc = ((Baud<<(BaudGeneratorAccWidth-4))+(ClkFrequency>>5))/(ClkFrequency>>4);
	always @(posedge SysClk) BaudGeneratorAcc <= BaudGeneratorAcc[BaudGeneratorAccWidth-1:0] + BaudGeneratorInc;
   wire BaudTick = BaudGeneratorAcc[BaudGeneratorAccWidth];
	
	assign EnableTx = BaudTick;


endmodule
