`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   13:38:40 09/03/2007
// Design Name:   sram_iface
// Module Name:   sram_tb.v
// Project Name:  DLX
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: sram_iface
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module sram_tb_v;

	// Inputs
	reg clk_i;
	reg reset_i;
	reg [31:0] data_i;
	reg [31:0] addr_i;
	reg Breq_i;
	reg WR_i;

	// Outputs
	wire [31:0] data_o;
	wire reqp_o;
	wire Brdy_o;
	wire [21:0] mem_addr;
	wire [3:0] sram_bs;
	wire sram_cs;
	wire flash_cs;
	wire mem_we;
	wire mem_oe;

	// Bidirs
	wire [31:0] mem_d;

	// Instantiate the Unit Under Test (UUT)
	sram_iface uut (
		.clk_i(clk_i), 
		.reset_i(reset_i), 
		.data_i(data_i), 
		.data_o(data_o), 
		.addr_i(addr_i), 
		.Breq_i(Breq_i), 
		.WR_i(WR_i), 
		.reqp_o(reqp_o), 
		.Brdy_o(Brdy_o), 
		.mem_d(mem_d), 
		.mem_addr(mem_addr), 
		.sram_bs(sram_bs), 
		.sram_cs(sram_cs), 
		.flash_cs(flash_cs), 
		.mem_we(mem_we), 
		.mem_oe(mem_oe)
	);

	initial begin
		// Initialize Inputs
		clk_i = 0;
		reset_i = 1;
		data_i = 0;
		addr_i = 0;
		Breq_i = 0;
		WR_i = 0;

		// Wait 100 ns for global reset to finish
		#100;
		reset_i = 0;
        
		// Add stimulus here

		@(posedge clk_i) Breq_i <= 1;
		@(posedge clk_i) Breq_i <= 0;
		@(posedge clk_i);
		@(posedge clk_i) addr_i = addr_i + 1;
		@(posedge clk_i);
		@(posedge clk_i) Breq_i <= 1;
		@(posedge clk_i) Breq_i <= 0;
		@(posedge clk_i);
		@(posedge clk_i) addr_i = 32'h800002;
		@(posedge clk_i);
		@(posedge clk_i) Breq_i <= 1;
		@(posedge clk_i) Breq_i <= 0;

	end
      
		always #5 clk_i = !clk_i;
		
endmodule

