@inproceedings{Tverdyshev:TIME08-??, <br>AUTHOR = {Tverdyshev, S. and Alkassar, E.},<br>TITLE = {Efficient Bit-Level Model Reductions for Automated Hardware Verification},<br>YEAR = {2008},<br>PAGES = {pp. 164-172}, <br>BOOKTITLE = {15th International Symposium on Temporal Representation and Reasoning: TIME2008}, <br>PUBLISHER = {IEEE Computer Society Press},<br>EDITOR = {Stéphane Demri and Christian S. Jensen},<br>EE = {http://doi.ieeecomputersociety.org/10.1109/TIME.2008.11 },<br>}