`include "inc.h" //******************************************************************************* // S Y N T H E Z I A B L E S D R A M C O N T R O L L E R C O R E // // This core adheres to the GNU Public License // // This is a synthesizable Synchronous DRAM controller Core. As it stands, // it is ready to work with 8Mbyte SDRAMs, organized as 2M x 32 at 100MHz // and 125MHz. For example: Samsung KM432S2030CT, Fujitsu MB81F643242B. // // The core has been carefully coded so as to be "platform-independent". // It has been successfully compiled and simulated under three separate // FPGA/CPLD platforms: // Xilinx Foundation Base Express V2.1i // Altera Max+PlusII V9.21 // Lattice ispExpert V7.0 // // The interface to the host (i.e. microprocessor, DSP, etc) is synchronous // and supports ony one transfer at a time. That is, burst-mode transfers // are not yet supported. In may ways, the interface to this core is much // like that of a typical SRAM. The hand-shaking between the host and the // SDRAM core is done through the "sdram_busy_l" signal generated by the // core. Whenever this signal is active low, the host must hold the address, // data (if doing a write), size and the controls (cs, rd/wr). // // // Author: Jeung Joon Lee joon.lee@quantum.com, cmosexod@ix.netcom.com // // modified by : Dirk Leinenbach dirkl@wjpserver.cs.uni-sb.de // //******************************************************************************* // // Hierarchy: // // SDRAM.V Top Level Module // HOSTCONT.V Controls the interfacing between the micro and the SDRAM // SDRAMCNT.V This is the SDRAM controller. All data passed to and from // is with the HOSTCONT. // optional // MICRO.V This is the built in SDRAM tester. This module generates // a number of test logics which is used to test the SDRAM // It is basically a Micro bus generator. // /* */ module sdram( // SYSTEM LEVEL CONNECTIONS sys_rst_l, sys_clk, // SDRAM CONNECTIONS sd_wr_l, sd_cs_l, sd_ras_l, sd_cas_l, sd_dqm0, sd_dqm1, sd_dqm2, sd_dqm3, sd_addx, sd_data0, sd_data1, sd_data2, sd_data3, sd_ba, // MICROPORCESSOR CONNECTION mp_addx, mp_data_in, mp_data_out, mp_rd_l, mp_wr_l, mp_cs_l, sdram_mode_set_l, sdram_busy_l, mp_mask, next_state ); // **************************************** // // I/O DEFINITION // // **************************************** // SYSTEM LEVEL CONNECTIONS input sys_clk; // global system clock. Runs the sdram state machine input sys_rst_l; // global active low asynchronous system reset // SDRAM CONNECTIONS output sd_wr_l; // SDRAM active low WRITE signal output sd_cs_l; // SDRAM active low chip select signal output sd_ras_l; // SDRAM active low RAS output sd_cas_l; // SDRAM active low CAS output [1:0] sd_dqm0; // SDRAM data masks output [1:0] sd_dqm1; // SDRAM data masks output [1:0] sd_dqm2; // SDRAM data masks output [1:0] sd_dqm3; // SDRAM data masks output [11:0] sd_addx; // SDRAM multiplexed address bus inout [15:0] sd_data0; // SDRAM birectional data bus 32 bit inout [15:0] sd_data1; // SDRAM birectional data bus 32 bit inout [15:0] sd_data2; // SDRAM birectional data bus 32 bit inout [15:0] sd_data3; // SDRAM birectional data bus 32 bit output [1:0] sd_ba; // SDRAM bank address , aka A11 // MICROPROCESSOR CONNECTION input [63:0] mp_data_in; output [63:0] mp_data_out; input [22:0] mp_addx; // HOST address bus. 23 bits for 8Mb input mp_rd_l; // HOST active low READ input mp_wr_l; // HOST active low WRITE input mp_cs_l; // HOST active low chip select input sdram_mode_set_l; input [7:0] mp_mask; output sdram_busy_l; output [3:0] next_state; // INTER-MODULE CONNECTIONS wire do_modeset; wire do_read; wire do_write; wire doing_refresh; wire sd_addx_ena; wire [1:0] sd_addx_mux; wire [1:0] sd_addx10_mux; wire sd_rd_ena; wire sd_data_ena; wire [2:0] modereg_cas_latency; wire [2:0] modereg_burst_length; wire [3:0] next_state; wire [63:0] mp_data_out_sd; wire [63:0] mp_data_in; //wire [15:0] sd_data; wire mp_cs_l; wire mp_wr_l; wire mp_rd_l; wire mp_data_mux; wire [3:0] autorefresh_cntr; wire autorefresh_cntr_l; wire pwrup; wire [3:0] top_state; wire [22:0] reg_mp_addx; wire [1:0] decoded_dqm0; wire [1:0] decoded_dqm1; wire [1:0] decoded_dqm2; wire [1:0] decoded_dqm3; wire do_write_ack; wire do_read_ack; wire do_modeset_ack; wire [63:0] reg_mp_data_mux; wire [15:0] sd_data_in0; wire [15:0] sd_data_in1; wire [15:0] sd_data_in2; wire [15:0] sd_data_in3; wire [15:0] sd_data_out0; wire [15:0] sd_data_out1; wire [15:0] sd_data_out2; wire [15:0] sd_data_out3; wire [15:0] reg_sd_data0; wire [15:0] reg_sd_data1; wire [15:0] reg_sd_data2; wire [15:0] reg_sd_data3; wire sdram_mode_set_l; wire sys_clk; wire sdram_busy_l; wire mp_data_gate; // // HOST sie DATA BUS DRISVERS // // // assign mp_data_gate = (~mp_rd_l & ~mp_cs_l); // --- Unidirectional Data bus Mos assign mp_data_out = mp_data_gate ? mp_data_out_sd : 64'h0000000000000000; // // SDRAM side bidirectional data bus drivers //assign sd_data = sd_data_ena ? sd_data_out : 16'hzzzzzzzz; // bufif1 b0_0 (sd_data0[0], sd_data_out0[0], sd_data_ena); bufif1 b1_0 (sd_data0[1], sd_data_out0[1], sd_data_ena); bufif1 b2_0 (sd_data0[2], sd_data_out0[2], sd_data_ena); bufif1 b3_0 (sd_data0[3], sd_data_out0[3], sd_data_ena); bufif1 b4_0 (sd_data0[4], sd_data_out0[4], sd_data_ena); bufif1 b5_0 (sd_data0[5], sd_data_out0[5], sd_data_ena); bufif1 b6_0 (sd_data0[6], sd_data_out0[6], sd_data_ena); bufif1 b7_0 (sd_data0[7], sd_data_out0[7], sd_data_ena); bufif1 b8_0 (sd_data0[8], sd_data_out0[8], sd_data_ena); bufif1 b9_0 (sd_data0[9], sd_data_out0[9], sd_data_ena); bufif1 b10_0 (sd_data0[10], sd_data_out0[10], sd_data_ena); bufif1 b11_0 (sd_data0[11], sd_data_out0[11], sd_data_ena); bufif1 b12_0 (sd_data0[12], sd_data_out0[12], sd_data_ena); bufif1 b13_0 (sd_data0[13], sd_data_out0[13], sd_data_ena); bufif1 b14_0 (sd_data0[14], sd_data_out0[14], sd_data_ena); bufif1 b15_0 (sd_data0[15], sd_data_out0[15], sd_data_ena); assign sd_data_in0 = sd_data0; bufif1 b0_1 (sd_data1[0], sd_data_out1[0], sd_data_ena); bufif1 b1_1 (sd_data1[1], sd_data_out1[1], sd_data_ena); bufif1 b2_1 (sd_data1[2], sd_data_out1[2], sd_data_ena); bufif1 b3_1 (sd_data1[3], sd_data_out1[3], sd_data_ena); bufif1 b4_1 (sd_data1[4], sd_data_out1[4], sd_data_ena); bufif1 b5_1 (sd_data1[5], sd_data_out1[5], sd_data_ena); bufif1 b6_1 (sd_data1[6], sd_data_out1[6], sd_data_ena); bufif1 b7_1 (sd_data1[7], sd_data_out1[7], sd_data_ena); bufif1 b8_1 (sd_data1[8], sd_data_out1[8], sd_data_ena); bufif1 b9_1 (sd_data1[9], sd_data_out1[9], sd_data_ena); bufif1 b10_1 (sd_data1[10], sd_data_out1[10], sd_data_ena); bufif1 b11_1 (sd_data1[11], sd_data_out1[11], sd_data_ena); bufif1 b12_1 (sd_data1[12], sd_data_out1[12], sd_data_ena); bufif1 b13_1 (sd_data1[13], sd_data_out1[13], sd_data_ena); bufif1 b14_1 (sd_data1[14], sd_data_out1[14], sd_data_ena); bufif1 b15_1 (sd_data1[15], sd_data_out1[15], sd_data_ena); assign sd_data_in1 = sd_data1; bufif1 b0_2 (sd_data2[0], sd_data_out2[0], sd_data_ena); bufif1 b1_2 (sd_data2[1], sd_data_out2[1], sd_data_ena); bufif1 b2_2 (sd_data2[2], sd_data_out2[2], sd_data_ena); bufif1 b3_2 (sd_data2[3], sd_data_out2[3], sd_data_ena); bufif1 b4_2 (sd_data2[4], sd_data_out2[4], sd_data_ena); bufif1 b5_2 (sd_data2[5], sd_data_out2[5], sd_data_ena); bufif1 b6_2 (sd_data2[6], sd_data_out2[6], sd_data_ena); bufif1 b7_2 (sd_data2[7], sd_data_out2[7], sd_data_ena); bufif1 b8_2 (sd_data2[8], sd_data_out2[8], sd_data_ena); bufif1 b9_2 (sd_data2[9], sd_data_out2[9], sd_data_ena); bufif1 b10_2 (sd_data2[10], sd_data_out2[10], sd_data_ena); bufif1 b11_2 (sd_data2[11], sd_data_out2[11], sd_data_ena); bufif1 b12_2 (sd_data2[12], sd_data_out2[12], sd_data_ena); bufif1 b13_2 (sd_data2[13], sd_data_out2[13], sd_data_ena); bufif1 b14_2 (sd_data2[14], sd_data_out2[14], sd_data_ena); bufif1 b15_2 (sd_data2[15], sd_data_out2[15], sd_data_ena); assign sd_data_in2 = sd_data2; bufif1 b0_3 (sd_data3[0], sd_data_out3[0], sd_data_ena); bufif1 b1_3 (sd_data3[1], sd_data_out3[1], sd_data_ena); bufif1 b2_3 (sd_data3[2], sd_data_out3[2], sd_data_ena); bufif1 b3_3 (sd_data3[3], sd_data_out3[3], sd_data_ena); bufif1 b4_3 (sd_data3[4], sd_data_out3[4], sd_data_ena); bufif1 b5_3 (sd_data3[5], sd_data_out3[5], sd_data_ena); bufif1 b6_3 (sd_data3[6], sd_data_out3[6], sd_data_ena); bufif1 b7_3 (sd_data3[7], sd_data_out3[7], sd_data_ena); bufif1 b8_3 (sd_data3[8], sd_data_out3[8], sd_data_ena); bufif1 b9_3 (sd_data3[9], sd_data_out3[9], sd_data_ena); bufif1 b10_3 (sd_data3[10], sd_data_out3[10], sd_data_ena); bufif1 b11_3 (sd_data3[11], sd_data_out3[11], sd_data_ena); bufif1 b12_3 (sd_data3[12], sd_data_out3[12], sd_data_ena); bufif1 b13_3 (sd_data3[13], sd_data_out3[13], sd_data_ena); bufif1 b14_3 (sd_data3[14], sd_data_out3[14], sd_data_ena); bufif1 b15_3 (sd_data3[15], sd_data_out3[15], sd_data_ena); assign sd_data_in3 = sd_data3; // // INSTANTIATE THE SDRAM STATE MACHINE // sdramcnt MYSDRAMCNT( // system level stuff .sys_rst_l(sys_rst_l), .sys_clk(sys_clk), // SDRAM connections .sd_wr_l(sd_wr_l), .sd_cs_l(sd_cs_l), .sd_ras_l(sd_ras_l), .sd_cas_l(sd_cas_l), .sd_dqm0(sd_dqm0), .sd_dqm1(sd_dqm1), .sd_dqm2(sd_dqm2), .sd_dqm3(sd_dqm3), // Host Controller connections .do_mode_set(do_modeset), .do_read(do_read), .do_write(do_write), .doing_refresh(doing_refresh), .sd_addx_mux(sd_addx_mux), .sd_addx10_mux(sd_addx10_mux), .sd_rd_ena(sd_rd_ena), .sd_data_ena(sd_data_ena), .modereg_cas_latency(modereg_cas_latency), .modereg_burst_length(modereg_burst_length), .mp_data_mux(mp_data_mux), .decoded_dqm0(decoded_dqm0), .decoded_dqm1(decoded_dqm1), .decoded_dqm2(decoded_dqm2), .decoded_dqm3(decoded_dqm3), .do_write_ack(do_write_ack), .do_read_ack(do_read_ack), .do_modeset_ack(do_modeset_ack), .pwrup(pwrup), // debug .next_state(next_state), .autorefresh_cntr(autorefresh_cntr), .autorefresh_cntr_l(autorefresh_cntr_l) ); // // INSTANTIATE THE HOST INTERFACE LOGIC // hostcont MYHOSTCONT( // system connections .sys_rst_l(sys_rst_l), .sys_clk(sys_clk), // microprocessor side connections .mp_addx(mp_addx), .mp_data_in(mp_data_in), .mp_data_out(mp_data_out_sd), .mp_rd_l(mp_rd_l), .mp_wr_l(mp_wr_l), .mp_cs_l(mp_cs_l), .sdram_mode_set_l(sdram_mode_set_l), .sdram_busy_l(sdram_busy_l), .mp_mask(mp_mask), // SDRAM side connections .sd_addx(sd_addx), .sd_data_in0(sd_data0), .sd_data_in1(sd_data1), .sd_data_in2(sd_data2), .sd_data_in3(sd_data3), .sd_data_out0(sd_data_out0), .sd_data_out1(sd_data_out1), .sd_data_out2(sd_data_out2), .sd_data_out3(sd_data_out3), .sd_ba(sd_ba), // SDRAMCNT side .sd_addx10_mux(sd_addx10_mux), .sd_addx_mux(sd_addx_mux), .sd_rd_ena(sd_rd_ena), .do_read(do_read), .do_write(do_write), .doing_refresh(doing_refresh), .do_modeset(do_modeset), .modereg_cas_latency(modereg_cas_latency), .modereg_burst_length(modereg_burst_length), .mp_data_mux(mp_data_mux), .decoded_dqm0(decoded_dqm0), .decoded_dqm1(decoded_dqm1), .decoded_dqm2(decoded_dqm2), .decoded_dqm3(decoded_dqm3), .do_write_ack(do_write_ack), .do_read_ack(do_read_ack), .do_modeset_ack(do_modeset_ack), .pwrup(pwrup), // debug .reg_mp_data_mux(reg_mp_data_mux), .reg_mp_addx(reg_mp_addx), .reg_sd_data0(reg_sd_data0), .reg_sd_data1(reg_sd_data1), .reg_sd_data2(reg_sd_data2), .reg_sd_data3(reg_sd_data3) ); endmodule