// synopsys translate_off
`include "C_DIST_MEM_V1_0.v"
// synopsys translate_on

module GPR(clk,radr_A, radr_B, wadr, din, we, dout_A, dout_B);
   input         clk;
   input [4:0]         radr_A;
   input [4:0]         radr_B;
   input [4:0]         wadr;
   input [31:0]  din;
   input       we;
   output [31:0] dout_A;
   output [31:0] dout_B;
   wire [31:0]         ignoreme;
   wire [31:0]         ignoreme2;

   // instantiation of dualport RAMs
   gpr_ram gpr_ram1 (
                   .A(wadr),
                   .CLK(clk),
                   .D(din),
                   .WE(we),
                   .DPRA(radr_A),
                   .DPO(dout_A),
                   .SPO(ignoreme));
   gpr_ram gpr_ram2 (
                   .A(wadr),
                   .CLK(clk),
                   .D(din),
                   .WE(we),
                   .DPRA(radr_B),
                   .DPO(dout_B),
                   .SPO(ignoreme2));

endmodule // GPR

module data_ram(clk,adr, din, we, dout);
   input         clk;
   input [8:0]   adr;

   input [7:0]  din;
   input       we;
   output [7:0] dout;

   cache_data_ram data_ram1 (
			     .addra(adr),
			     .addrb(adr),
			     .clka(clk),
			     .clkb(~clk),
			     .dina(din),
			     .doutb(dout),
			     .wea(we));
   
endmodule // data_ram

module valid_ram(clk,adr, din, we, dout);
   input         clk;
   input [6:0]   adr;

   input 	 din;
   input 	 we;
   output 	 dout;

   cache_valid_ram valid_ram1 (
			       .addra(adr),
			       .addrb(adr),
			       .clka(clk),
			       .clkb(~clk),
			       .dina(din),
			       .doutb(dout),
			       .wea(we));

endmodule // valid_ram


module tag_ram(clk,adr, din, we, dout);
   input         clk;
   input [6:0]   adr;

   input [19:0]	 din;
   input 	 we;
   output [19:0] dout;

   cache_tag_ram tag_ram1 (
			   .addra(adr),
			   .addrb(adr),
			   .clka(clk),
			   .clkb(~clk),
			   .dina(din),
			   .doutb(dout),
			   .wea(we));

endmodule // tag_ram


module history_ram1(clk, radr, wadr, din, we, dout);
   input         clk;
   input [6:0]   radr;
   input [6:0] 	 wadr;   

   input [1:0]	 din;
   input 	 we;
   output [1:0]	 dout;

   cache_history_ram1 history_ram1 (
				    .addra(wadr),
				    .addrb(radr),
				    .clka(clk),
				    .clkb(~clk),
				    .dina(din),
				    .doutb(dout),
				    .wea(we));
   
endmodule // history_ram1

module history_ram2(clk, radr, wadr, din, we, dout);
   input         clk;
   input [6:0]   radr;
   input [6:0] 	 wadr;   

   input [7:0]	 din;
   input 	 we;
   output [7:0]	 dout;

   cache_history_ram2 history_ram2 (
				    .addra(wadr),
				    .addrb(radr),
				    .clka(clk),
				    .clkb(~clk),
				    .dina(din),
				    .doutb(dout),
				    .wea(we));
   
endmodule // history_ram2

module FPR_half(clk, radr_A, radr_B, wadr, din, we, dout_A, dout_B);
   input         clk;
   input [3:0]         radr_A;
   input [3:0]         radr_B;
   input [3:0]         wadr;
   input [31:0]  din;
   input       we;
   output [31:0] dout_A;
   output [31:0] dout_B;

   wire [31:0]         ignoreme;
   wire [31:0]         ignoreme2;

   // instatiation of dualport RAMs
   fprhalf_ram fprhalf_ram1 (
                           .A(wadr),
                           .CLK(clk),
                           .D(din),
                           .WE(we),
                           .DPRA(radr_A),
                           .DPO(dout_A),
                           .SPO(ignoreme));
   fprhalf_ram fprhalf_ram2 (
                           .A(wadr),
                           .CLK(clk),
                           .D(din),
                           .WE(we),
                           .DPRA(radr_B),
                           .DPO(dout_B),
                           .SPO(ignoreme2));
endmodule // FPR_half

module gpr_ram (
              A,
              CLK,
              D,
              WE,
              DPRA,
              DPO,
              SPO);

   input [4 : 0]   A;
   input         CLK;
   input [31 : 0]  D;
   input         WE;
   input [4 : 0]   DPRA;
   output [31 : 0] DPO;
   output [31 : 0] SPO;

   // synopsys translate_off

   C_DIST_MEM_V1_0 #(
                   5,
                   "0",
                   32,
                   1,
                   1,
                   1,
                   1,
                   1,
                   1,
                   0,
                   0,
                   0,
                   0,
                   0,
                   0,
                   0,
                   1,
                   0,
                   1,
                   "gpr_ram.mif",
                   1,
                   2,
                   0,
                   0,
                   1,
                   0,
                   0,
                   0,
                   0,
                   32)
   inst (
       .A(A),
       .CLK(CLK),
       .D(D),
       .WE(WE),
       .DPRA(DPRA),
       .DPO(DPO),
       .SPO(SPO));

   // synopsys translate_on

endmodule // gpr_ram

module fprhalf_ram (
                  A,
                  CLK,
                  D,
                  WE,
                  DPRA,
                  DPO,
                  SPO);

   input [3 : 0]   A;
   input         CLK;
   input [31 : 0]  D;
   input         WE;
   input [3 : 0]   DPRA;
   output [31 : 0] DPO;
   output [31 : 0] SPO;

   // synopsys translate_off

   C_DIST_MEM_V1_0 #(
                   4,
                   "0",
                   16,
                   1,
                   1,
                   1,
                   1,
                   1,
                   1,
                   0,
                   0,
                   0,
                   0,
                   0,
                   0,
                   0,
                   1,
                   0,
                   1,
                   "fprhalf_ram.mif",
                   1,
                   2,
                   0,
                   0,
                   1,
                   0,
                   0,
                   0,
                   0,
                   32)
   inst (
       .A(A),
       .CLK(CLK),
       .D(D),
       .WE(WE),
       .DPRA(DPRA),
       .DPO(DPO),
       .SPO(SPO));
   // synopsys translate_on
endmodule // fprhalf_ram


module mult_lin_30_30(clk,a_0x,a_1x,out_2x);
	input clk;
	input [29:0] a_0x;	// external name: a
	input [29:0] a_1x;	// external name: b
	output [59:0] out_2x;	// external name: out`

   assign 	      out_2x=a_0x * a_1x;
   
endmodule

module mult_lin_29_29(clk,a_0x,a_1x,out_2x);
	input clk;
	input [28:0] a_0x;	// external name: a
	input [28:0] a_1x;	// external name: b
	output [57:0] out_2x;	// external name: out`

   
   assign 	      out_2x=a_0x*a_1x;
   
endmodule

module basicadder_impl_29(clk,a_0x,a_1x,a_2x,out_3x);
	input clk;
	input [28:0] a_0x;	// external name: a
	input [28:0] a_1x;	// external name: b
	input a_2x;	// external name: cin
	output [29:0] out_3x;	// external name: out`

   assign 	      out_3x=a_0x+a_1x+a_2x;

endmodule // basicadder_impl_29

module basicadder_impl_58(clk,a_0x,a_1x,a_2x,out_3x);
	input clk;
	input [57:0] a_0x;	// external name: a
	input [57:0] a_1x;	// external name: b
	input a_2x;	// external name: cin
	output [58:0] out_3x;	// external name: out`

   assign out_3x=a_0x+a_1x+a_2x;
   
endmodule

module basicadder_impl_61(clk,a_0x,a_1x,a_2x,out_3x);
	input clk;
	input [60:0] a_0x;	// external name: a
	input [60:0] a_1x;	// external name: b
	input a_2x;	// external name: cin
	output [61:0] out_3x;	// external name: out`

   assign out_3x=a_0x+a_1x+a_2x;

endmodule // basicadder_implx_61

module basicadder_impl_118(clk,a_0x,a_1x,a_2x,out_3x);
	input clk;
	input [117:0] a_0x;	// external name: a
	input [117:0] a_1x;	// external name: b
	input a_2x;	// external name: cin
	output [118:0] out_3x;	// external name: out`

   assign 	       out_3x=a_0x+a_1x+a_2x;
endmodule // basicadder_implx_118

module basicadder_impl_117(clk,a_0x,a_1x,a_2x,out_3x);
	input clk;
	input [116:0] a_0x;	// external name: a
	input [116:0] a_1x;	// external name: b
	input a_2x;	// external name: cin
	output [117:0] out_3x;	// external name: out'
   
   assign 	       out_3x=a_0x+a_1x+a_2x;
endmodule // basicadder_impl_117

module carry_chain_impl_13(clk,a_0x,a_1x,a_2x,out_3x);
	input clk;
	input [12:0] a_0x;	// external name: a
	input [12:0] a_1x;	// external name: b
	input a_2x;	// external name: cin
	output [13:0] out_3x;	// external name: out'
   
   assign 	       out_3x=a_0x+a_1x+a_2x;
endmodule // carry_chain_impl_13

module carry_chain_impl_54(clk,a_0x,a_1x,a_2x,out_3x);
	input clk;
	input [53:0] a_0x;	// external name: a
	input [53:0] a_1x;	// external name: b
	input a_2x;	// external name: cin
	output [54:0] out_3x;	// external name: out'
   
   assign 	       out_3x=a_0x+a_1x+a_2x;
endmodule // carry_chain_impl_54

module carry_chain_impl_12(clk,a_0x,a_1x,a_2x,out_3x);
	input clk;
	input [11:0] a_0x;	// external name: a
	input [11:0] a_1x;	// external name: b
	input a_2x;	// external name: cin
	output [12:0] out_3x;	// external name: out'
   
   assign 	       out_3x=a_0x+a_1x+a_2x;
endmodule // carry_chain_impl_12

module carry_chain_impl_11(clk,a_0x,a_1x,a_2x,out_3x);
	input clk;
	input [10:0] a_0x;	// external name: a
	input [10:0] a_1x;	// external name: b
	input a_2x;	// external name: cin
	output [11:0] out_3x;	// external name: out'
   
   assign 	      out_3x=a_0x+a_1x+a_2x;
endmodule // carry_chain_impl_11

module incr_impl_53(clk,a_0x,a_1x,out_2x);
   input clk;
   input [52:0] a_0x;
   input 	a_1x;
   output [53:0] out_2x;

   assign 	 out_2x=(a_1x==1) ? a_0x+1:a_0x;
   
endmodule // incr_impl_55

module incr_impl_11(clk,a_0x,a_1x,out_2x);
   input clk;
   input [10:0] a_0x;
   input 	a_1x;
   output [11:0] out_2x;
   
   assign 	 out_2x=(a_1x==1) ? a_0x+1:a_0x;
   
endmodule // incr_impl_11

module incr_impl_8(clk,a_0x,a_1x,out_2x);
   input clk;
   input [7:0] a_0x;
   input       a_1x;
   output [8:0] out_2x;
   
   assign 	out_2x=(a_1x==1) ? a_0x+1:a_0x;
   
endmodule // incr_impl_8

module incr_impl_33(clk,a_0x,a_1x,out_2x);
   input clk;
   input [32:0] a_0x;
   input 	a_1x;
   output [33:0] out_2x;
   
   assign 	 out_2x=(a_1x==1) ? a_0x+1:a_0x;
   
endmodule // incr_impl_33

module incr_impl_31(clk,a_0x,a_1x,out_2x);
   input clk;
   input [30:0] a_0x;
   input 	a_1x;
   output [31:0] out_2x;

   assign 	 out_2x=(a_1x==1) ? a_0x+1:a_0x;
	 
endmodule // incr_impl_31

module incr_impl_55(clk,a_0x,a_1x,out_2x);
   input clk;
   input [54:0] a_0x;
   input 	a_1x;
   output [55:0] out_2x;

   assign 	 out_2x=(a_1x==1) ? a_0x+1:a_0x;
	 
endmodule // incr_impl_55

module incr_impl_57(clk,a_0x,a_1x,out_2x);
   input clk;
   input [56:0] a_0x;
   input 	a_1x;
   output [57:0] out_2x;

   assign 	 out_2x=(a_1x==1) ? a_0x+1:a_0x;
	 
endmodule // incr_impl_55

module or_tree_impl_5_5(clk,a,o);
   input clk;
   input [4:0] a;
   output      o;

   assign      o=|(a);
endmodule // or_tree_impl_5_5

module or_tree_impl_6_6(clk,a,o);
   input clk;
   input [5:0] a;
   output      o;

   assign      o=|(a);
endmodule // or_tree_impl_6_6

module or_tree_impl_7_7(clk,a,o);
   input clk;
   input [6:0] a;
   output      o;

   assign      o=|(a);
endmodule // or_tree_impl_7_7

module or_tree_impl_8_8(clk,a,o);
   input clk;
   input [7:0] a;
   output      o;

   assign      o=|(a);
endmodule // or_tree_impl_8_8

module or_tree_impl_9_9(clk,a,o);
   input clk;
   input [8:0] a;
   output      o;

   assign      o=|(a);
endmodule // or_tree_impl_9_9

module or_tree_impl_11_11(clk,a,o);
   input clk;
   input [10:0] a;
   output      o;

   assign      o=|(a);
endmodule // or_tree_impl_11_11

module or_tree_impl_13_13(clk,a,o);
   input clk;
   input [12:0] a;
   output      o;

   assign      o=|(a);
endmodule // or_tree_impl_13_13

module or_tree_impl_21_21(clk,a,o);
   input clk;
   input [20:0] a;
   output      o;

   assign      o=|(a);
endmodule // or_tree_impl_21_21

module or_tree_impl_32_32(clk,a,o);
   input clk;
   input [31:0] a;
   output      o;

   assign      o=|(a);
endmodule // or_tree_impl_32_32

module or_tree_impl_52_52(clk,a,o);
   input clk;
   input [51:0] a;
   output      o;

   assign      o=|(a);
endmodule // or_tree_impl_52_52

module or_tree_impl_53_53(clk,a,o);
   input clk;
   input [52:0] a;
   output      o;

   assign      o=|(a);
endmodule // or_tree_impl_53_53

module or_tree_impl_54_54(clk,a,o);
   input clk;
   input [53:0] a;
   output      o;

   assign      o=|(a);
endmodule // or_tree_impl_54_54

module or_tree_impl_55_55(clk,a,o);
   input clk;
   input [54:0] a;
   output      o;

   assign      o=|(a);
endmodule // or_tree_impl_55_55

module or_tree_impl_60_60(clk,a,o);
   input clk;
   input [59:0] a;
   output      o;

   assign      o=|(a);
endmodule // or_tree_impl_60_60

module or_tree_impl_63_63(clk,a,o);
   input clk;
   input [62:0] a;
   output      o;

   assign      o=|(a);
endmodule // or_tree_impl_63_63

module or_tree_impl_74_74(clk,a,o);
   input clk;
   input [73:0] a;
   output      o;

   assign      o=|(a);
endmodule // or_tree_impl_74_74

module or_tree_impl_103_103(clk,a,o);
   input clk;
   input [102:0] a;
   output      o;

   assign      o=|(a);
endmodule // or_tree_impl_103_103

module or_tree_impl_117_117(clk,a,o);
   input clk;
   input [116:0] a;
   output      o;

   assign      o=|(a);
endmodule // or_tree_impl_117_117

module equal_impl_5(clk,a,b,o);
   input clk;
   input [4:0] a;
   input [4:0] b;
   output      o;

   assign      o= (a==b) ? 1:0;
endmodule // equal_impl_5

module equal_impl_9(clk,a,b,o);
   input clk;
   input [8:0] a;
   input [8:0] b;
   output      o;

   assign      o= (a==b) ? 1:0;
endmodule // equal_impl_9

module equal_impl_11(clk,a,b,o);
   input clk;
   input [10:0] a;
   input [10:0] b;
   output      o;

   assign      o= (a==b) ? 1:0;
endmodule // equal_impl_11

module equal_impl_13(clk,a,b,o);
   input clk;
   input [12:0] a;
   input [12:0] b;
   output      o;

   assign      o= (a==b) ? 1:0;
endmodule // equal_impl_13

module equal_impl_53(clk,a,b,o);
   input clk;
   input [52:0] a;
   input [52:0] b;
   output      o;

   assign      o= (a==b) ? 1:0;
endmodule // equal_impl_53

module equal_impl_64(clk,a,b,o);
   input clk;
   input [63:0] a;
   input [63:0] b;
   output      o;

   assign      o= (a==b) ? 1:0;
endmodule // equal_impl_64

module zero_impl_7(clk,a,o);
   input clk;
   input [6:0] a;
   output      o;

   assign      o= (a==0) ? 1:0;
endmodule // zero_impl_7

module zero_impl_8(clk,a,o);
   input clk;
   input [7:0] a;
   output      o;

   assign      o= (a==0) ? 1:0;
endmodule // zero_impl_8

module zero_impl_11(clk,a,o);
   input clk;
   input [10:0] a;
   output      o;

   assign      o= (a==0) ? 1:0;
endmodule // zero_impl_11

module zero_impl_21(clk,a,o);
   input clk;
   input [20:0] a;
   output      o;

   assign      o= (a==0) ? 1:0;
endmodule // zero_impl_21

module zero_impl_32(clk,a,o);
   input clk;
   input [31:0] a;
   output      o;

   assign      o= (a==0) ? 1:0;
endmodule // zero_impl_32

module zero_impl_52(clk,a,o);
   input clk;
   input [51:0] a;
   output      o;

   assign      o= (a==0) ? 1:0;
endmodule // zero_impl_52

module zero_impl_54(clk,a,o);
   input clk;
   input [53:0] a;
   output      o;

   assign      o= (a==0) ? 1:0;
endmodule // zero_impl_54

module zero_impl_63(clk,a,o);
   input clk;
   input [62:0] a;
   output      o;

   assign      o= (a==0) ? 1:0;
endmodule // zero_impl_63

module zero_impl_74(clk,a,o);
   input clk;
   input [73:0] a;
   output 	o;
   
   assign 	o = (a==0) ? 1:0;
endmodule // zero_impl_74

module zero_impl_103(clk,a,o);
   input clk;
   input [102:0] a;
   output 	 o;
   
   assign 	 o = (a==0) ? 1:0;
endmodule // zero_impl_103