/*******************************************************************
* This file was created by the Xilinx CORE Generator tool, and     *
* is (c) Xilinx, Inc. 1998, 1999. No part of this file may be      *
* transmitted to any third party (other than intended by Xilinx)   *
* or used without a Xilinx programmable or hardwire device without *
* Xilinx's prior written permission.                               *
*******************************************************************/ 

// The following line must appear at the top of the file in which
// the core instantiation will be made. Ensure that the translate_off/_on
// compiler directives are correct for your synthesis tool(s)

// Your Verilog compiler/interpreter might require the following
// option or it's equivalent to help locate the Xilinx Core Library
// +incdir+${XILINX}/verilog/src
// Here ${XILINX} refers to the XILINX software installation directory.

//----------- Begin Cut here for LIBRARY inclusion --------// LIB_TAG

// synopsys translate_off

`include "C_DIST_MEM_V1_0.v"

// synopsys translate_on

// LIB_TAG_END ------- End LIBRARY inclusion --------------

// The following code must appear after the module in which it
// is to be instantiated. Ensure that the translate_off/_on compiler
// directives are correct for your synthesis tool(s).

//----------- Begin Cut here for MODULE Declaration -------// MOD_TAG
module gpr_ram (
	A,
	CLK,
	D,
	WE,
	DPRA,
	DPO,
	SPO);

input [4 : 0] A;
input CLK;
input [31 : 0] D;
input WE;
input [4 : 0] DPRA;
output [31 : 0] DPO;
output [31 : 0] SPO;

// synopsys translate_off

	C_DIST_MEM_V1_0 #(
		5,
		"0",
		32,
		1,
		1,
		1,
		1,
		1,
		1,
		0,
		0,
		0,
		0,
		0,
		0,
		0,
		1,
		0,
		1,
		"gpr_ram.mif",
		1,
		2,
		0,
		0,
		1,
		0,
		0,
		0,
		0,
		32)
	inst (
		.A(A),
		.CLK(CLK),
		.D(D),
		.WE(WE),
		.DPRA(DPRA),
		.DPO(DPO),
		.SPO(SPO));

// synopsys translate_on

endmodule

// MOD_TAG_END ------- End MODULE Declaration -------------

// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.

//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
gpr_ram YourInstanceName (
	.A(A),
	.CLK(CLK),
	.D(D),
	.WE(WE),
	.DPRA(DPRA),
	.DPO(DPO),
	.SPO(SPO));

// INST_TAG_END ------ End INSTANTIATION Template ---------