----------------------------------------------------------------------
-- This file was created by the Xilinx CORE Generator tool, and     --
-- is (c) Xilinx, Inc. 1998, 1999. No part of this file may be      --
-- transmitted to any third party (other than intended by Xilinx)   --
-- or used without a Xilinx programmable or hardwire device without --
-- Xilinx's prior written permission.                               --
----------------------------------------------------------------------

-- The following code must appear in the VHDL architecture header:

------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
component div_lookup
	port (
	A: IN std_logic_VECTOR(7 downto 0);
	SPO: OUT std_logic_VECTOR(7 downto 0));
end component;

-- COMP_TAG_END ------ End COMPONENT Declaration ------------

-- The following code must appear in the VHDL architecture
-- body. Substitute your own instance name and net names.

------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
your_instance_name : div_lookup
		port map (
			A => A,
			SPO => SPO);
-- INST_TAG_END ------ End INSTANTIATION Template ------------

-- The following code must appear above the VHDL configuration
-- declaration. An example is given at the end of this file.

------------- Begin Cut here for LIBRARY Declaration -------- LIB_TAG

-- synopsys translate_off

Library XilinxCoreLib;

-- synopsys translate_on

-- LIB_TAG_END ------- End LIBRARY Declaration ------------

-- The following code must appear within the VHDL top-level
-- configuration declaration. Ensure that the translate_off/on
-- compiler directives are correct for your synthesis tool(s).

------------- Begin Cut here for CONFIGURATION snippet ------ CONF_TAG

-- synopsys translate_off

	for all : div_lookup use entity XilinxCoreLib.C_DIST_MEM_V1_0(behavioral)
		generic map(
			c_reg_dpra_input => 0,
			c_has_spo => 1,
			c_has_dpra => 0,
			c_reg_a_d_inputs => 0,
			c_has_qdpo_ce => 0,
			c_width => 8,
			c_has_qdpo_clk => 0,
			c_has_qspo => 0,
			c_addr_width => 8,
			c_has_spra => 0,
			c_has_dpo => 0,
			c_has_i_ce => 0,
			c_qce_joined => 1,
			c_has_we => 0,
			c_has_clk => 0,
			c_has_d => 0,
			c_mux_type => 0,
			c_read_mif => 1,
			c_qualify_we => 0,
			c_depth => 256,
			c_pipe_stages => 0,
			c_has_qdpo => 0,
			c_has_rd_en => 0,
			c_mem_type => 0,
			c_mem_init_radix => 1,
			c_has_qspo_ce => 0,
			c_default_data => "0",
			c_mem_init_file => "div_lookup.mif",
			c_generate_mif => 1,
			c_enable_rlocs => 1);
	end for;

-- synopsys translate_on

-- CONF_TAG_END ------ End CONFIGURATION snippet ------------

-------------------------------------------------------------
-- Example of configuration declaration...
-------------------------------------------------------------
--
-- <Insert LIBRARY Declaration here>
--
-- configuration <cfg_my_design> of <my_design> is
--     for <my_arch_name>
--         <Insert CONFIGURATION Declaration here>
--     end for;
-- end <cfg_my_design>;
--
-- If this is not the top-level design then in the next level up, the following text
-- should appear at the end of that file:
--
-- configuration <cfg> of <next_level> is
--     for <arch_name>
--           for all : <my_design> use configuration <cfg_my_design>;
--           end for;
--     end for;
-- end <cfg>;
--