/*******************************************************************
* This file is owned and controlled by Xilinx and must be used     *
* solely for design, simulation, implementation and creation of    *
* design files limited to Xilinx devices or technologies. Use      *
* with non-Xilinx devices or technologies is expressly prohibited  *
* and immediately terminates your license.                         *
*                                                                  *
* Xilinx products are not intended for use in life support         *
* appliances, devices, or systems. Use in such applications are    *
* expressly prohibited.                                            *
*                                                                  *
* Copyright (C) 2001, Xilinx, Inc.  All Rights Reserved.           *
*******************************************************************/ 

// The synopsys directives "translate_off/translate_on" specified
// below are supported by XST, FPGA Express, Exemplar and Synplicity
// synthesis tools. Ensure they are correct for your synthesis tool(s).

// You must compile the wrapper file cache_data_ram.v when simulating
// the core, cache_data_ram. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "Coregen Users Guide".

module cache_data_ram (
	addra,
	addrb,
	clka,
	clkb,
	dina,
	doutb,
	wea);

input [8 : 0] addra;
input [8 : 0] addrb;
input clka;
input clkb;
input [7 : 0] dina;
output [7 : 0] doutb;
input wea;

// synopsys translate_off

	BLKMEMDP_V3_1 #(
		9,	// c_addra_width
		9,	// c_addrb_width
		"00",	// c_default_data
		512,	// c_depth_a
		512,	// c_depth_b
		0,	// c_family
		1,	// c_has_default_data
		1,	// c_has_dina
		0,	// c_has_dinb
		0,	// c_has_douta
		1,	// c_has_doutb
		0,	// c_has_ena
		0,	// c_has_enb
		0,	// c_has_limit_data_pitch
		0,	// c_has_nda
		0,	// c_has_ndb
		0,	// c_has_rdya
		0,	// c_has_rdyb
		0,	// c_has_rfda
		0,	// c_has_rfdb
		0,	// c_has_sinita
		0,	// c_has_sinitb
		1,	// c_has_wea
		0,	// c_has_web
		18,	// c_limit_data_pitch
		"mif_file_16_1",	// c_mem_init_file
		0,	// c_pipe_stages_a
		0,	// c_pipe_stages_b
		0,	// c_reg_inputsa
		0,	// c_reg_inputsb
		"00",	// c_sinita_value
		"00",	// c_sinitb_value
		8,	// c_width_a
		8,	// c_width_b
		0,	// c_write_modea
		0)	// c_write_modeb
	inst (
		.ADDRA(addra),
		.ADDRB(addrb),
		.CLKA(clka),
		.CLKB(clkb),
		.DINA(dina),
		.DOUTB(doutb),
		.WEA(wea));


// synopsys translate_on

endmodule