//////////////////////////////////////////////////////////////////////
//                                                                  //
// VERILOG LIBRARY                                                  //
//                                                                  //
// 64Mbit-SDRAM ( 4Bank x 4096Row x 256Col x 16bit ) MB811641642A   //
//         ONLY 1N FUNCTION                                         //
//         OUTPUT TIMING LVTTL                                      //
//                                                                  //
//   Copyright (c) FUJITSU LIMITED, 1995,1996.                      //
//   All Rights Reserved. Licensed Library.                         //
//                                                                  //
//  History                                                         //
//   Rev.  Reg.-No.  Date         Comment                           //
// MB811641642A                                                     //
//   1.00  95RV-001 1995/12/08   First  Release Version.            //
//   1.01  95RV-002 1996/01/06   2nd Version                        //
//   2.00  96RV-003 1996/09/30   3nd Version                        //
//                                                                  //
//////////////////////////////////////////////////////////////////////
// `timescale 100ps / 100ps

`celldefine
module SDRAM64Mx16(
  DQ15,DQ14,DQ13,DQ12,DQ11,DQ10,DQ9,DQ8,
  DQ7,DQ6,DQ5,DQ4,DQ3,DQ2,DQ1,DQ0,
  A13,A12,A11,A10,A9,A8,A7,A6,A5,A4,A3,A2,A1,A0,
  CLK,CKE,RAS,CAS,WE,CS,DQMU,DQML
  );

  
  inout    DQ15,DQ14,DQ13,DQ12,DQ11,DQ10,DQ9,DQ8,
           DQ7,DQ6,DQ5,DQ4,DQ3,DQ2,DQ1,DQ0;
  
  input A13,A12,A11,A10,A9,A8,A7,A6,A5,A4,A3,A2,A1,A0;
  
  input CLK,CKE,RAS,CAS,WE,CS,DQMU,DQML ;



parameter SPEED_VERSION = 8 ;


parameter ERROR_STOP = 0 ;  


`protect



parameter PASSWORD_for_SECURITY = "abcdefg" ;


parameter INIT_CL=3 ;  
parameter INIT_BT=0 ;  
parameter INIT_BL=0 ;  


parameter LCKE=1 ; 
parameter LDQZ=2 ; 
parameter LDQD=0 ; 
parameter LOWD=2 ; 
parameter LDWD=0 ; 

parameter LMRD=2 ; 
parameter LCCD=1 ; 
parameter LCBD=1 ; 
parameter LRWL=1 ; 
parameter LRRL=1 ; 


parameter NUM_of_BANK =4 ;      
parameter NUM_of_ROW  =4096 ;   
parameter NUM_of_COL  =256 ;

parameter WIDTH_of_DATA=16 ;
parameter WIDTH_of_ADDRESS=14 ; 
parameter WIDTH_of_BAD=2 ;      
parameter WIDTH_of_RAD=12;      
parameter WIDTH_of_CAD=8;


parameter WIDTH_of_DQM=2;
parameter UNIT_of_DQM=8;


parameter MODE_REGISTER_READ = 1 ; 
parameter NUM_of_MRR =4;  


parameter OP_CODE    = 1 ; 
parameter FULL_BURST = 1 ; 
parameter INIT_OP=0 ;  
parameter FULL_BURST_AP = 01 ; 


parameter PIN_BS2=13 , PIN_BS1=12 , PIN_PC=10;  


parameter MAX_CL=3;


parameter sdram64mx16_debug = 0 ;  


  integer i,j,k ;  
  integer ERR_CODE;
  integer ERR_PARM;
  reg iCLK , oCLK ;
  reg[WIDTH_of_DATA-1:0] OUTCTL;
  reg PC;  

  wire [WIDTH_of_ADDRESS-1:0] A ={A13,A12,A11,A10,A9,A8,A7,A6,A5,A4,A3,A2,A1,A0} ;
  wire [WIDTH_of_DATA-1:0]  D ;
  reg  [WIDTH_of_DATA-1:0]  Q,WRITE_DATA,Q_WK ;

  
  wire [WIDTH_of_DQM-1:0] DQMS = {DQMU,DQML} ;
  
  reg [WIDTH_of_DQM-1:0] DQE[MAX_CL:0] ;
  reg [WIDTH_of_DQM-1:0] DQE0,DQE1 ;

  
  reg [LCKE:0] HLD_CKE ;

  
  reg [WIDTH_of_DATA-1:0] iQ ;
  reg [WIDTH_of_DATA-1:0] OQ[MAX_CL:0] ;
  reg [MAX_CL:0] OUT_FLAG ;
  reg [WIDTH_of_DATA-1:0] PREV_OUT_FLAG ;	
  reg [MAX_CL:0] MRR_FLAG;
  reg [NUM_of_BANK -1:0] BCF[MAX_CL:0] ; 
  reg [LOWD:0] OWD_CTL ; 	
  reg [LRWL:0] RWL_CTL ; 		
  reg [LRRL:0] RRL_CTL ;		

  reg [MAX_CL:0] PD_PRT ;   

  
  reg [WIDTH_of_DATA -1:0] mem[NUM_of_BANK * NUM_of_ROW * NUM_of_COL -1:0] ;
  reg [WIDTH_of_DATA -1:0] old_mem ;

  
  reg [WIDTH_of_BAD + WIDTH_of_RAD + WIDTH_of_CAD -1:0] ADD ;
  reg [WIDTH_of_BAD -1:0] BAD,BS ;    
  reg [WIDTH_of_RAD -1:0] RAD[NUM_of_BANK -1:0]; 
  reg [WIDTH_of_CAD -1:0] CAD,CAD_S,CAD_U;  

  
  reg[3:0]  CMD;    

  
  reg      OP_REG;  
  reg[2:0] BL_REG;  
  reg      BT_REG;  
  reg[2:0] CL_REG;  
  reg[2:0] RFU_REG;  
  reg[WIDTH_of_CAD:0] BURST_LENGTH;  

  
  reg[WIDTH_of_CAD-1:0] BL_CNT;  
  reg[1:0] MRD_CNT  ;  

  
  reg [4:0] old_BANK_STAT;
  reg [4:0] BANK_STAT[NUM_of_BANK -1:0] ;
  
  
  
  
  
  
  
  
  
  reg [NUM_of_BANK -1:0] ACTV_STAT,READ_STAT,WRTE_STAT,PCHG_STAT,REFR_STAT;
  reg [NUM_of_BANK -1:0] LAST_READ ;
  reg [WIDTH_of_BAD-1:0] REF_BANK ;     
  reg PD_STAT , SREF_STAT, SREF_RECV ;  
  reg OUTPUT_COMPLETE ;
  reg MODE_REG_READ;
  reg [MAX_CL:0]WA_FLAG;	
  reg [WIDTH_of_BAD -1:0] WA_BAD;			
  reg [MAX_CL:0]RA_FLAG;	
  reg [WIDTH_of_BAD -1:0] RA_BAD;			

  
  reg [63:0] T_PCHG_OUT[NUM_of_BANK -1:0] ;  
  reg [63:0] T_CAC[MAX_CL:0] ;  
  real T_OVC,T_OVC_NOW ;
  reg [63:0] T_AUTO_REF_IN[NUM_of_BANK -1:0];  
  reg [63:0] T_CKE_RISE ;  
  reg [63:0] T_LAST_WRITE[NUM_of_BANK -1:0] ;  
  reg [63:0] T_PD_ENTER ;
  reg [63:0] T_BANK_ACTIVE[NUM_of_BANK -1:0] ;


  reg [63:0] TRC  ; 
  reg [63:0] TRAC ; 
  reg [63:0] TCAC ; 
  reg [63:0] TRP  ; 
  reg [63:0] TRAS_MIN ,TRAS_MAX ; 
  reg [63:0] TRCD ; 
  reg [63:0] TWR  ; 
  reg [63:0] TRWL ; 
  reg [63:0] TRRD ; 

  reg [63:0] TPDE ; 
  reg [63:0] TAC[1:MAX_CL] ; 
  reg [63:0] TOLZ ; 
  reg [63:0] TOHZ_MAX[1:MAX_CL] ; 
  reg [63:0] TOH  ; 
  reg [63:0] TLZ  ; 
  reg [63:0] THZ_MAX[1:MAX_CL]  ; 

  reg [63:0] TREF ; 

  reg [63:0] TCLK[1:MAX_CL] ;  
  reg [63:0] LAST_CLK,NEXT_CLK ;
  
  reg [63:0] TCH,TCL  ;  
  reg [63:0] TSC,THC  ;  
  reg [63:0] TSI,THI  ;  
  
  reg  [63:0]  T_CLK_RISE ;  
  reg  [63:0]  T_CLK_FALL ;  
  reg  [63:0]  T_TRAN_ADD ;  
  reg  [63:0]  T_TRAN_DIN ;  
  reg  [63:0]  T_TRAN_CKE ;  
  reg  [63:0]  T_TRAN_CMD ;  
  reg  [63:0]  T_TRAN_CSL ;  
  reg  [63:0]  T_TRAN_DQM ;  
  

  event WARNING ;  
  event ILLEGAL ;  
  event ILLEGAL_CKE ;  
  event ILLEGAL_TIMING ; 
  event ILLEGAL_OPE ; 



  bufif1 dq_out00(DQ0  ,Q[  0],OUTCTL[ 0]) ;
  bufif1 dq_out01(DQ1  ,Q[  1],OUTCTL[ 1]) ;
  bufif1 dq_out02(DQ2  ,Q[  2],OUTCTL[ 2]) ;
  bufif1 dq_out03(DQ3  ,Q[  3],OUTCTL[ 3]) ;
  bufif1 dq_out04(DQ4  ,Q[  4],OUTCTL[ 4]) ;
  bufif1 dq_out05(DQ5  ,Q[  5],OUTCTL[ 5]) ;
  bufif1 dq_out06(DQ6  ,Q[  6],OUTCTL[ 6]) ;
  bufif1 dq_out07(DQ7  ,Q[  7],OUTCTL[ 7]) ;
  bufif1 dq_out08(DQ8  ,Q[  8],OUTCTL[ 8]) ;
  bufif1 dq_out09(DQ9  ,Q[  9],OUTCTL[ 9]) ;
  bufif1 dq_out10(DQ10,Q[10],OUTCTL[10]) ;
  bufif1 dq_out11(DQ11,Q[11],OUTCTL[11]) ;
  bufif1 dq_out12(DQ12,Q[12],OUTCTL[12]) ;
  bufif1 dq_out13(DQ13,Q[13],OUTCTL[13]) ;
  bufif1 dq_out14(DQ14,Q[14],OUTCTL[14]) ;
  bufif1 dq_out15(DQ15,Q[15],OUTCTL[15]) ;

//  tran    dq_in00(D[ 0],DQ0 ) ;
//  tran    dq_in01(D[ 1],DQ1 ) ;
//  tran    dq_in02(D[ 2],DQ2 ) ;
//  tran    dq_in03(D[ 3],DQ3 ) ;
//  tran    dq_in04(D[ 4],DQ4 ) ;
//  tran    dq_in05(D[ 5],DQ5 ) ;
//  tran    dq_in06(D[ 6],DQ6 ) ;
//  tran    dq_in07(D[ 7],DQ7 ) ;
//  tran    dq_in08(D[ 8],DQ8 ) ;
//  tran    dq_in09(D[ 9],DQ9 ) ;
//  tran    dq_in10(D[10],DQ10) ;
//  tran    dq_in11(D[11],DQ11) ;
//  tran    dq_in12(D[12],DQ12) ;
//  tran    dq_in13(D[13],DQ13) ;
//  tran    dq_in14(D[14],DQ14) ;
//  tran    dq_in15(D[15],DQ15) ;

  buf    dq_in00(D[ 0],DQ0 ) ;
  buf    dq_in01(D[ 1],DQ1 ) ;
  buf    dq_in02(D[ 2],DQ2 ) ;
  buf    dq_in03(D[ 3],DQ3 ) ;
  buf    dq_in04(D[ 4],DQ4 ) ;
  buf    dq_in05(D[ 5],DQ5 ) ;
  buf    dq_in06(D[ 6],DQ6 ) ;
  buf    dq_in07(D[ 7],DQ7 ) ;
  buf    dq_in08(D[ 8],DQ8 ) ;
  buf    dq_in09(D[ 9],DQ9 ) ;
  buf    dq_in10(D[10],DQ10) ;
  buf    dq_in11(D[11],DQ11) ;
  buf    dq_in12(D[12],DQ12) ;
  buf    dq_in13(D[13],DQ13) ;
  buf    dq_in14(D[14],DQ14) ;
  buf    dq_in15(D[15],DQ15) ;


  initial
    begin
      $timeformat(-9, 1 , "ns",10);
      if(PASSWORD_for_SECURITY != "abcdefg") begin
        $write("Error!    ") ;
        $display("Too many module instance parameter assignments\n") ;
        $finish ;
      end

       
      case(SPEED_VERSION)
        8 : begin
          TCLK[3]=80  ; TCLK[2]=120 ; TCLK[1]=240 ;
          TCH =35 ; TCL =35 ;
          TSC =25 ; THC =10 ; TSI =25 ; THI =10 ;
          TAC[3]=75  ; TAC[2]=90  ; TAC[1]=220 ;
          TOLZ=20 ; TOH=20 ;
	  TOHZ_MAX[3]=80 ;TOHZ_MAX[2]=120 ;TOHZ_MAX[1]=240 ;	
          TREF=656000000 ; 
          TRC = 770 ; TRAC=450 ; TCAC=210 ; TRP=290 ;
          TRAS_MIN=480 ; TRAS_MAX=1000000 ;
          TRCD=240 ; TWR=80 ; TRWL=80 ; TRRD=240 ;
          TPDE=30 ;
        end
        10 : begin
          TCLK[3]=100 ; TCLK[2]=150 ; TCLK[1]=300 ;
          TCH =35 ; TCL =35 ;
          TSC =30 ; THC =10 ; TSI =30 ; THI =10 ;
          TAC[3]= 85 ; TAC[2]=90  ; TAC[1]=280 ;  
          TOLZ=30  ; TOH=30 ;
          TOHZ_MAX[3]=100 ; TOHZ_MAX[2]=150 ; TOHZ_MAX[1]=300 ;	
          TREF=656000000 ; 
          TRC = 900  ; TRAC=540 ; TCAC=240 ; TRP=300 ; 
          TRAS_MIN=600 ; TRAS_MAX=1000000 ;
          TRCD=300 ; TWR=100 ; TRWL=100 ; TRRD=300 ;
          TPDE=30 ;
        end
        12 : begin
          TCLK[3]=120 ; TCLK[2]=170 ; TCLK[1]=350 ;
          TCH =40 ; TCL =40 ;
          TSC =30 ; THC =10 ; TSI =30 ; THI =10 ;
          TAC[3]=85 ; TAC[2]=100 ; TAC[1]=310 ;
          TOLZ=30  ; TOH=30 ;
          TOHZ_MAX[3]=120 ; TOHZ_MAX[2]=170 ; TOHZ_MAX[1]=350 ;	
          TREF=656000000 ; 
          TRC = 1000 ; TRAC=560 ; TCAC=260 ; TRP=350 ;
          TRAS_MIN=650 ; TRAS_MAX=1000000 ;
          TRCD=300 ; TWR=120 ; TRWL=120 ; TRRD=300 ;
          TPDE=40 ;
        end
        15 : begin
          TCLK[3]=150 ; TCLK[2]=200 ; TCLK[1]=400 ;
          TCH =40 ; TCL =40 ;
          TSC =30 ; THC =10 ; TSI =30 ; THI =10 ;
          TAC[3]=90 ; TAC[2]=100 ; TAC[1]=340 ;
          TOLZ=30  ; TOH=30 ;
          TOHZ_MAX[3]=150 ; TOHZ_MAX[2]=200 ; TOHZ_MAX[1]=400 ;	
          TREF=656000000 ; 
          TRC =1100 ; TRAC=600 ; TCAC=300 ; TRP=400 ;
          TRAS_MIN=700 ; TRAS_MAX=1000000 ;
          TRCD=300 ; TWR=150 ; TRWL=150 ; TRRD=300 ;
          TPDE=50 ;
        end
        default : begin  
          $write("Invalid value for Speed-Version %0d\n",SPEED_VERSION) ;
          $finish ;
        end
      endcase





       
      if(sdram64mx16_debug == 1) begin
        $write(" Speed(%0d)\n",SPEED_VERSION) ;
        $write("  tCLK[3,2,1]=(%0t,%0t,%0t)\n",TCLK[3],TCLK[2],TCLK[1]) ;
        $write("  TCH =%0t TCL =%0t",TCH,TCL) ;
        $write(" TSC =%0t THC =%0t TSI =%0t THI =%0t\n",TSC,THC,TSI,THI) ;
        $write("  tAC[3,2,1]=(%0t,%0t,%0t)",TAC[3],TAC[2],TAC[1]) ;
        $write(" TOLZ=%0t TOHZ=%0t TOH=%0t\n",TOLZ,TOHZ_MAX[3],TOH) ;
        $write("  TREF=%0t TPDE=%0t",TREF,TPDE) ;
        $write(" TRC=%0t TRAC=%0t TCAC=%0t TRP=%0t\n",TRC,TRAC,TCAC,TRP) ;
        $write("  TRAS(MIX,MAX)=(%0t,%0t)",TRAS_MIN,TRAS_MAX) ;
        $write(" TRCD=%0t TWR=%0t TRWL=%0t TRRD=%0t\n",TRCD,TWR,TRWL,TRRD) ;
      end

      CL_REG = INIT_CL ; BT_REG = INIT_BT ;
      BL_REG=INIT_BL ;  BURST_LENGTH = 1 ;
      if( OP_CODE == "1") OP_REG = INIT_OP ;
      else                OP_REG = 0 ;
      T_OVC  = TAC[CL_REG] ;

      for(i=0;i<NUM_of_BANK;i=i+1) begin
        RAD[i] = {WIDTH_of_RAD{1'b0}} ;
        BANK_STAT[i] = 0 ;
        T_LAST_WRITE[i] = 0 ;
      end
      CAD = 0 ; CAD_S =  0 ;  CAD_U = 0;

      MRD_CNT = LMRD ;
      BL_CNT = 0 ;
      OUTCTL = 0 ;
      PREV_OUT_FLAG = 0 ;

      for(i=0;i<=MAX_CL;i=i+1) begin
        OQ[i] = {WIDTH_of_DATA{1'bz}} ;
        OUT_FLAG[i] = 0 ;
        MRR_FLAG[i] = 0 ;
        PD_PRT[i] = 0 ;
	WA_FLAG[i]=0;		
	RA_FLAG[i]=0;		
      end
      for(i=0;i<=LCKE;i=i+1) begin
        HLD_CKE[i] = 1'b1 ;
      end
      ACTV_STAT = 0 ;  READ_STAT = 0 ;  WRTE_STAT = 0 ;  PCHG_STAT = 0 ;
      OUTPUT_COMPLETE = 1 ;  MODE_REG_READ = 0 ;
      REF_BANK = 1 ; REFR_STAT = 0 ;
      SREF_STAT = 0 ; SREF_RECV = 0 ; PD_STAT = 0 ;
      LAST_CLK = 0 ; NEXT_CLK = 0 ;

      T_CLK_FALL = 0 ; T_CLK_RISE = 0 ;
      T_TRAN_ADD = 0 ; T_TRAN_DIN = 0 ; T_TRAN_CMD = 0 ;
      T_TRAN_CKE = 0 ; T_TRAN_CSL = 0 ; T_TRAN_DQM = 0 ;
    end

  
  
  
  
  
  
  always @(posedge CLK) begin : CLK_RISE
    LAST_CLK =  T_CLK_RISE ;		
    T_CLK_RISE = $time ;
    
    if( T_CLK_RISE > T_CLK_FALL ) begin
      if( T_CLK_FALL + TCL > $time ) begin
        ERR_CODE=1007;
        ->WARNING;
        
      end
      
      if( T_TRAN_ADD + TSI > $time )  begin
        ERR_CODE=1008;
        ->WARNING;
      end
        
      if( T_TRAN_DIN + TSI > $time ) begin
	if(OWD_CTL == 0) begin
        ERR_CODE=1009;
        ->WARNING;
end
      end
        
      if( T_TRAN_CMD + TSI  > $time && OUT_FLAG == 0) begin	
       ERR_CODE=1010;
       ->WARNING;
      end
        
      if( T_TRAN_CKE + TSI  > $time ) begin
        ERR_CODE=1011;
        ->WARNING;
      end
        
      if( T_TRAN_DQM + TSI  > $time ) begin
        ERR_CODE=1012;
        ->WARNING;
      end
        
      if( T_TRAN_CSL + TSC  > $time ) begin
        ERR_CODE=1013;
        ->WARNING;
      end
        
    end
    

    for(i=0;i<LCKE;i=i+1) begin
      HLD_CKE[i] = HLD_CKE[i + 1] ;
    end
    HLD_CKE[LCKE] = CKE ;










    
    CMD = {CS,RAS,CAS,WE};
    if(CMD > 4'b0111) begin
      CMD = 4'b0111 ;  
    end

    
    if(PD_STAT == 1) begin
      if(CKE == 1) begin
        if((T_CKE_RISE + TPDE) <= $time) begin
          PD_STAT = 0 ;
        end  
        if(CMD < 4'b0111) begin
          ERR_CODE=1501;
          
          -> ILLEGAL_TIMING ;  
        end
      end  

      else if( (PD_STAT == 1) && ((T_PD_ENTER + TREF < $time))) begin
        ERR_CODE=1502;
        
        -> ILLEGAL_TIMING ;  
      end
      disable CLK_RISE;
    end  

    
    if(SREF_STAT == 1) begin
      if(CKE == 1) begin
        if((T_CKE_RISE + TPDE) <= $time) begin
          if(CMD >= 4'b0111) begin  
            for(i=0;i<NUM_of_BANK;i=i+1) begin
              T_AUTO_REF_IN[i] = $time ;
              BANK_STAT[i] = 5'b10000 ;
              REFR_STAT[i] = 1 ;
            end
            SREF_STAT = 0 ;
            SREF_RECV = 1 ;
          end  
          else begin
            ERR_CODE=1503;
            
            -> ILLEGAL_TIMING ;  
          end
        end  
        else if(CMD < 4'b0110) begin
          ERR_CODE=1504;
          
          -> ILLEGAL_TIMING ;  
        end
      end  
      disable CLK_RISE;
    end  
    

    
    if(MRD_CNT < LMRD) begin
      MRD_CNT = MRD_CNT +1 ;
    end

    
    if(HLD_CKE[0] == 1)      iCLK = 1;
  end

  always @(negedge CLK) begin : CLK_FALL
    T_CLK_FALL = $time ;
    if( (T_CLK_FALL > T_CLK_RISE) && (T_CLK_RISE + TCH > $time) ) begin
      ERR_CODE=1014;
      ->WARNING;
      
    end

    iCLK = 0; oCLK = 0;
  end

  always @(posedge CKE) begin : CKE_RISE
    
    T_CKE_RISE = $time ;
    
  end

  always @(posedge iCLK) begin : INTERNAL_CLOCK 
    if(T_CKE_RISE < LAST_CLK) begin
      if($time < (LAST_CLK + TCLK[CL_REG] )) begin

        
        ERR_CODE=1505;
        -> ILLEGAL_TIMING ;  
        
      end
    end
      NEXT_CLK = $time + TCLK[CL_REG] ;


      PD_PRT  = PD_PRT >>1 ;  
      WA_FLAG = WA_FLAG >>1;	
      RA_FLAG = RA_FLAG >>1;	

    for(i=0;i<NUM_of_BANK;i=i+1) begin 
      case(BANK_STAT[i])
        4'b1000: begin  
	  if(WA_FLAG > 0) begin			
	    if(WA_FLAG == 1) begin		
              PRECHG_SET(T_PCHG_OUT[WA_BAD],BANK_STAT[WA_BAD],T_BANK_ACTIVE[WA_BAD]) ;
	    end
	  end					
	  else begin				
          if(T_PCHG_OUT[i] <= $time ) begin
            BANK_STAT[i] = 4'b0000 ;
            PCHG_STAT[i] = 1'b0 ;
          end
	  end
        end  
        5'b10000: begin  
          if( (T_AUTO_REF_IN[i] + TRC) <= $time) begin
            BANK_STAT[i] = 0 ;
            REFR_STAT[i] = 0 ;
            if(SREF_RECV == 1) SREF_RECV = 0 ;
          end
        end  
      endcase

      
      if(ACTV_STAT[i] == 1) begin
        if(T_BANK_ACTIVE[i] + TRAS_MAX < $time) begin
          ERR_CODE=1506;
          ERR_PARM=i;
          
          -> ILLEGAL_TIMING ;  
        end
      end

      
      
      
        if(BANK_STAT[i] == 4'b1001) begin
          PRECHG_SET(T_PCHG_OUT[i],BANK_STAT[i],T_BANK_ACTIVE[i]) ;
          {REFR_STAT[BAD],PCHG_STAT[BAD],
          WRTE_STAT[BAD],READ_STAT[BAD],ACTV_STAT[BAD]} = BANK_STAT[BAD];
          PD_PRT[CL_REG-1] = 1'b1 ;
        end
      
	if(RA_FLAG > 0) begin
	  if(RA_FLAG == 1) begin
            PRECHG_SET(T_PCHG_OUT[RA_BAD],BANK_STAT[RA_BAD],T_BANK_ACTIVE[RA_BAD]) ;
	  end
	end					
	    
    end  

    begin : COMMAND_DECODE
      BS = {A[PIN_BS2],A[PIN_BS1]} ;   
      PC = A[PIN_PC] ;

      OWD_CTL = OWD_CTL<<1 ;  
      RWL_CTL  = RWL_CTL>>1  ;  
 
      
      if(MRD_CNT < LMRD) begin
        if(CKE == 0) begin
          ERR_CODE=2001;
          
          -> ILLEGAL_CKE ;  
          disable COMMAND_DECODE ;
        end
        case(CMD)
          4'b0111: ;  
          default: begin
            ERR_CODE=2501;
            
            -> ILLEGAL_OPE ;  
            disable COMMAND_DECODE;
          end
        endcase
      end

      
      if(REFR_STAT != 0) begin
        if(CKE == 0) begin
          ERR_CODE=2002;
          
          -> ILLEGAL_CKE ;  
          disable COMMAND_DECODE ;
        end
        casex(CMD)
          4'b011?: ;  
          4'b0001: begin  
            if(SREF_RECV == 0) begin
              if(REFR_STAT == 15) begin  
                ERR_CODE=1507;
                
                -> ILLEGAL_TIMING ;  
                disable COMMAND_DECODE;
              end
              else begin
                if( (T_AUTO_REF_IN[0] + TRC) > $time) begin	
                 ERR_CODE=1507;						


                  
                  -> ILLEGAL_TIMING ;  
                  disable COMMAND_DECODE;
                end

    		for(i=0;i<NUM_of_BANK;i=i+1) begin 
                  T_AUTO_REF_IN[i] = $time;
                  BANK_STAT[i] = 5'b10000 ;
                  REFR_STAT[i] = 1 ;
		end
              end
            end 
            else begin  
              ERR_CODE=2502;
              
              -> ILLEGAL_OPE ;  
            end
          end  
          default: begin
            if(SREF_RECV == 1) begin
              ERR_CODE=2503;
              
              -> ILLEGAL_OPE ;  
            end
            else begin
             ERR_CODE=2504;
              
              -> ILLEGAL_OPE ;  
            end
          end
        endcase
        disable COMMAND_DECODE;
      end  

      
        
        
      if(CMD == 4'b0010) begin  
        for(i=0;i<NUM_of_BANK;i=i+1) begin
          if((PC == 1) || ((PC == 0) && (BS == i))) begin
            if( (T_LAST_WRITE[i] > 0)
                && (RWL_CTL > 0)) begin				

              ERR_CODE=1509;
              
              -> ILLEGAL_TIMING ;  
              disable COMMAND_DECODE ;
            end
            casex(BANK_STAT[i])
              4'b0000 : ;  
              4'b0001 : ; 
              4'b0011 : ; 
              4'b0101 : ;  
              4'b1000 : ;  
              default : begin
                ERR_CODE=3001;
                -> ILLEGAL ;
                disable COMMAND_DECODE ;
              end
            endcase
          end
        end    
        
        for(i=0;i<NUM_of_BANK;i=i+1) begin
          if((PC == 1) || ((PC == 0) && (BS == i))) begin
            casex(BANK_STAT[i])
              4'b0000 : begin 
		if(PC == 1)							
                  PRECHG_SET(T_PCHG_OUT[i],BANK_STAT[i],T_BANK_ACTIVE[i]) ;	
	      end
              4'b0001 : begin 
                PRECHG_SET(T_PCHG_OUT[i],BANK_STAT[i],T_BANK_ACTIVE[i]) ;
                
                
                
              end
              4'b0011 : begin 
                PRECHG_SET(T_PCHG_OUT[i],BANK_STAT[i],T_BANK_ACTIVE[i]) ;
                
                OUT_FLAG[CL_REG] = 0 ;
              end
              4'b0101 : begin  
                BANK_STAT[i] = 4'b0001 ;
                PRECHG_SET(T_PCHG_OUT[i],BANK_STAT[i],T_BANK_ACTIVE[i]) ;
              end
              4'b1000 : ;  
            endcase
            {REFR_STAT[i],PCHG_STAT[i],WRTE_STAT[i],READ_STAT[i],
            ACTV_STAT[i]} = BANK_STAT[i];
          end
        end  
      end  

      
      
      if(CKE == 0) begin : CKE_FUNCTION


        
        if( PD_PRT > 4'b0001 ) disable CKE_FUNCTION ;

        
        
        if( {REFR_STAT,ACTV_STAT,PCHG_STAT} == 0) begin
          case(CMD)
            4'b0111 : PD_STAT = 1 ;
            4'b0010 : PD_STAT = 1 ;  
            4'b0001 : SREF_STAT = 1 ;  
          endcase
        end  

        
        
        else if( ({REFR_STAT,ACTV_STAT} == 0) && (PCHG_STAT > 0)) begin
          
          if(OUT_FLAG > 1) begin
            $write("%t : Illegal CKE fall edge.",$time) ;
            $write("(Read Burst Incomplete)\n") ;
            -> ILLEGAL_CKE ;  
            disable COMMAND_DECODE ;
          end
          
          for(i=0;i<NUM_of_BANK;i=i+1) begin
            if(BANK_STAT[i] == 4'b1000) begin  
              if( ($time + TRP) < T_PCHG_OUT[i] ) begin
                ERR_CODE=2003;
                
                
                -> ILLEGAL_CKE ;  
                disable COMMAND_DECODE ;
              end
            end  
          end
          
          case(CMD)
            4'b0111 : PD_STAT = 1 ;  
            4'b0010 : PD_STAT = 1 ;  
          endcase
        end

        
        else if(ACTV_STAT > 0) begin
          if(ACTV_STAT < {NUM_of_BANK{1'b1}} ) begin
          
          
            for(i=0;i<NUM_of_BANK;i=i+1) begin

















              if(BANK_STAT[i] == 4'b1101) begin  
              
                if(( (BL_CNT + 1) == BURST_LENGTH) || (OP_REG == 1'b1)) begin
                  ERR_CODE=2004;
                  
                  
                  -> ILLEGAL_CKE ;  
                  disable COMMAND_DECODE ;
                end
              end  
            end  
          end  
          disable CKE_FUNCTION  ;    
        end 

        if(PD_STAT == 1) begin
          T_PD_ENTER = $time ;
          disable COMMAND_DECODE ;
        end
        if(SREF_STAT == 1) begin
          disable COMMAND_DECODE ;
        end
        ERR_CODE=2005;
        
        -> ILLEGAL_CKE ;
        disable COMMAND_DECODE ;
        
      end  








        case(CMD)
          4'b0000 : begin 
            if({ACTV_STAT,REFR_STAT,PCHG_STAT} == 0) begin
              
              if(A[7]==1)                  
              begin
                ERR_CODE=3002;
                -> ILLEGAL;  
              end
              else if(A[8] == 1) begin 
                if(MODE_REGISTER_READ == 1) begin
                  MRD_CNT = 0 ;  MODE_REG_READ = 1 ;
                end
                else
                  begin
                  ERR_CODE=3003;
                  -> ILLEGAL;  
                end
              end
              else begin 
                if( OP_CODE== 1 ) begin
                  OP_REG  = A[9] ;
                end
                else begin
                  if(A[WIDTH_of_ADDRESS -1:9] > 0)
                  begin
                    ERR_CODE=3004;
                   -> ILLEGAL ;  
                  end
                end
                  
                BT_REG  = A[3] ;
                RFU_REG = A[8:7] ;
                MRD_CNT = 0 ;

                
                case(A[2:0])
                  3'b000 : begin
                    BL_REG[2:0] = A[2:0] ;  BURST_LENGTH =   1;
                  end
                  3'b001 : begin
                    BL_REG[2:0] = A[2:0] ;  BURST_LENGTH =   2;
                  end
                  3'b010 : begin
                    BL_REG[2:0] = A[2:0] ;  BURST_LENGTH =   4;
                  end
                  3'b011 : begin
                    BL_REG[2:0] = A[2:0] ;  BURST_LENGTH =   8;
                  end
                  default: begin
                    if((A[2:0]==3'b111)&&(FULL_BURST==1)) begin  
                      BL_REG[2:0] = A[2:0] ;  BURST_LENGTH = NUM_of_COL;
                    end
                    else begin
                      
                      ERR_CODE=2505;
                      -> ILLEGAL_OPE ;  
                    end
                  end
                endcase

                case(A[6:4])




                  3'b010 : begin
                    CL_REG = 2 ; T_OVC  = TAC[2] ;
                  end
                  3'b011 : begin
                    CL_REG = 3 ; T_OVC  = TAC[3] ;
                  end
                  default: begin
                    
                    ERR_CODE=2506;
                    -> ILLEGAL_OPE ;  
                  end
                endcase

              end
            end
            else begin
              ERR_CODE=3013;
              -> ILLEGAL ;  
            end
          end  
          4'b0001 : begin 
            if({PCHG_STAT,WRTE_STAT,READ_STAT,ACTV_STAT} == 0) begin
              
              REF_BANK = REF_BANK + 1 ;
              for(i=0;i<NUM_of_BANK;i=i+1) begin
                T_AUTO_REF_IN[i] = $time;
                BANK_STAT[i] = 5'b10000 ;
                REFR_STAT[i] = 1'b1 ;
	      end
            end
            else begin
              ERR_CODE=3014;
              -> ILLEGAL;  
            end
          end
          4'b0010 : begin 
            
          end
          4'b0011 : begin 
            
            if(BANK_STAT[BS] == 4'b0000) begin
              
              for(i=0;i<NUM_of_BANK;i=i+1) begin
                if(ACTV_STAT[i] == 1'b1) begin
                  if( (T_BANK_ACTIVE[i] + TRRD) > $time) begin
                    
                    ERR_CODE=1510;
                    -> ILLEGAL_TIMING ;  
                    disable COMMAND_DECODE ;
                  end
                end
              end

              BANK_STAT[BS] = 4'b0001 ;
              RAD[BS] = A[WIDTH_of_RAD-1:0] ;
              T_BANK_ACTIVE[BS] = $time ;
            end
            else begin
              ERR_CODE=3005;
              -> ILLEGAL ;  
            end
          end
          4'b0100 : begin 
            
            
            
            if(OWD_CTL != 0) begin
              
              ERR_CODE=1511;
              -> ILLEGAL_TIMING ;  
              disable COMMAND_DECODE ;
            end
            
            if(ACTV_STAT[BS] == 1'b0) begin
              ERR_CODE=3006;
              -> ILLEGAL ;  
              disable COMMAND_DECODE ;
            end
            
            for(i=0;i<NUM_of_BANK;i=i+1) begin 
              if ((BANK_STAT[i] == 4'b1011) || (BANK_STAT[i] == 4'b1101)) begin
              
              ERR_CODE=3007;
                -> ILLEGAL ;  
                disable COMMAND_DECODE ;
              end
            end
            
            if((T_BANK_ACTIVE[BS] + TRCD) > $time) begin
              ERR_CODE=1512;
              
              
              -> ILLEGAL_TIMING ;  
              disable COMMAND_DECODE ;
            end
            
            if(BANK_STAT[BS] == 4'b1001) begin
              ERR_CODE=3008;
              -> ILLEGAL ;  
              disable COMMAND_DECODE ;
            end

            
            
            BANK_STAT[BS] = 4'b0101 ;
            CAD_S = A[WIDTH_of_CAD-1:0] ;



	    if(BL_REG != 3'b111)
              if(PC == 1) BANK_STAT[BS] = 4'b1101 ;  

            OUT_FLAG[MAX_CL:2]=0;    

            for(i=0;i<NUM_of_BANK;i=i+1) begin
              if(BS != i) begin        
                if ((BANK_STAT[i] == 4'b1011) || (BANK_STAT[i] == 4'b1101))
                  
                  PRECHG_SET(T_PCHG_OUT[i],BANK_STAT[i],T_BANK_ACTIVE[i]) ;
                else if ((BANK_STAT[i] == 4'b0011) || (BANK_STAT[i] == 4'b0101))
                  
                  BANK_STAT[i] = 4'b0001 ;
              end  
            end

            BAD = BS ;
            BL_CNT = 0 ;
          end
          4'b0101 : begin 
            
            
            if((T_LAST_WRITE[BS] + TWR) > $time) begin
              
              ERR_CODE=1513;
              -> ILLEGAL_TIMING ;  
              disable COMMAND_DECODE ;
            end
            
            if(ACTV_STAT[BS] == 1'b0) begin
              ERR_CODE=3009;
              -> ILLEGAL ;  
              disable COMMAND_DECODE ;
            end
            
            for(i=0;i<NUM_of_BANK;i=i+1) begin
              if ((BANK_STAT[i] == 4'b1011) || (BANK_STAT[i] == 4'b1101)) begin
              ERR_CODE=3010;
                -> ILLEGAL ;  
                disable COMMAND_DECODE ;
              end
            end
            
            if((T_BANK_ACTIVE[BS] + TRCD) > $time) begin
              
              ERR_CODE=1514;
              -> ILLEGAL_TIMING ;  
              disable COMMAND_DECODE ;
            end
            
            if(BANK_STAT[BS] == 4'b1001) begin
              ERR_CODE=3011;
              -> ILLEGAL ;  
              disable COMMAND_DECODE ;
            end

            
            
            BANK_STAT[BS] = 4'b0011 ;
            CAD_S = A[WIDTH_of_CAD-1:0] ;
	    if(BL_REG != 3'b111)
              if(PC == 1) BANK_STAT[BS] = 4'b1011 ;  

            for(i=0;i<NUM_of_BANK;i=i+1) begin
              if(BS != i) begin   
                if ((BANK_STAT[i] == 4'b1011) || (BANK_STAT[i] == 4'b1101))
                  
                  PRECHG_SET(T_PCHG_OUT[i],BANK_STAT[i],T_BANK_ACTIVE[i]) ;
                else if ((BANK_STAT[i] == 4'b0011) || (BANK_STAT[i] == 4'b0101))
                  
                  BANK_STAT[i] = 4'b0001 ;
              end
            end
  
            BAD = BS ;
            BL_CNT = 0 ;
          end
          4'b0110 : begin 
            if( FULL_BURST == 0 ) begin
              ERR_CODE=3012;
              -> ILLEGAL ;
            end
            
            for(i=0;i<NUM_of_BANK;i=i+1) begin
              case(BANK_STAT[i])
                5'b01000 : begin  
                  ERR_CODE=2509;
                  
                  -> ILLEGAL_OPE ;
                  disable COMMAND_DECODE ;
                end
              endcase
            end  
            
            for(i=0;i<NUM_of_BANK;i=i+1) begin
              casex(BANK_STAT[i])
                5'b0000? : ;  
                5'b00??1 : begin  
                  BANK_STAT[i] = 5'b00001 ;
                end
                5'b01011 : begin  


		  ERR_CODE=2509;
                  -> ILLEGAL_OPE ;
                end
                5'b01101 : begin  

		  ERR_CODE=2509;
                  -> ILLEGAL_OPE ;
                end
              endcase
            end  
          end
          4'b0111 : begin  
          end  
        endcase

        for(i=0;i<NUM_of_BANK;i=i+1) begin
          {REFR_STAT[i],PCHG_STAT[i],WRTE_STAT[i],READ_STAT[i],ACTV_STAT[i]} 
          = BANK_STAT[i];
          LAST_READ[i] = READ_STAT[i] ;
        end
      end  

      begin : DATA_ACCESS
        
        if((READ_STAT != 0) || (WRTE_STAT != 0)) begin
          
          if ((BT_REG == 0)||(BURST_LENGTH==1)||(BURST_LENGTH==NUM_of_COL))
            CAD_U = CAD_S + BL_CNT;  
          else
            CAD_U = CAD_S ^ BL_CNT;  

          
          BL_CNT = BL_CNT + 1 ;

          case(BURST_LENGTH)
            NUM_of_COL  : CAD =  CAD_U;
                  8  : CAD = {CAD_S[WIDTH_of_CAD -1:3],CAD_U[2:0]};
                  4  : CAD = {CAD_S[WIDTH_of_CAD -1:2],CAD_U[1:0]};
                  2  : CAD = {CAD_S[WIDTH_of_CAD -1:1],CAD_U[0]};
            default : CAD =  CAD_S[WIDTH_of_CAD -1:0];
          endcase

          ADD = {BAD,RAD[BAD],CAD} ;

          if(READ_STAT != 0) begin 
            
            READ_MEM(BAD,RAD[BAD],CAD,iQ) ; 
            
            OQ[CL_REG] = iQ ;
            OUT_FLAG[CL_REG] = 1 ;
            T_CAC[CL_REG] = $time + TCAC ;
          end
          else begin  
            OUTCTL = 0;

            if(DQMS != {WIDTH_of_DQM{1'b1}}) begin
              old_mem = mem[ADD] ;
              WRITE_DATA = D ;
              
              for(i=0;i<WIDTH_of_DQM;i=i+1) begin
                if(DQMS[i] == 1'b1) begin
                  for(j=i*UNIT_of_DQM;j<=(i+1)*UNIT_of_DQM-1;j=j+1)
                    WRITE_DATA[j] = old_mem[j] ;
                end
              end
              
              
              WRITE_MEM(BAD,RAD[BAD],CAD,WRITE_DATA) ; 
              T_LAST_WRITE[BAD] = $time ;
	      RWL_CTL[LRWL-1]=1'b1;		
            end

          end 

          if(BL_CNT >= BURST_LENGTH ||
             ((OP_REG == 1) && (WRTE_STAT !=0) && (OP_CODE == 1) )) begin
            BL_CNT = 0 ;
            
            if(READ_STAT != 0) begin
              READ_STAT = {NUM_of_BANK{1'b0}} ;
              
              case(CL_REG)
                1 : begin
			BCF[2] = {{NUM_of_BANK-1{1'b0}},1'b1}<<BAD ;
			if(PCHG_STAT[BAD] == 1'b1) RA_FLAG[LRRL]=1'b1;
		    end
                2 : begin
			BCF[2] = {{NUM_of_BANK-1{1'b0}},1'b1}<<BAD ;
			if(PCHG_STAT[BAD] == 1'b1) RA_FLAG[LRRL]=1'b1;
		    end
                3 : begin
			BCF[3] = {{NUM_of_BANK-1{1'b0}},1'b1}<<BAD ;
			if(PCHG_STAT[BAD] == 1'b1) RA_FLAG[LRRL+1]=1'b1;
		    end
              endcase
	      RA_BAD=BAD;			
            end

            
            if(WRTE_STAT != 0 ) begin
              WRTE_STAT = {NUM_of_BANK{1'b0}} ;
              if(PCHG_STAT[BAD] == 1'b1) begin
                PRECHG_SET(T_PCHG_OUT[BAD],BANK_STAT[BAD],T_BANK_ACTIVE[BAD]) ;
                {REFR_STAT[BAD],PCHG_STAT[BAD],
                WRTE_STAT[BAD],READ_STAT[BAD],ACTV_STAT[BAD]} = BANK_STAT[BAD];
		WA_FLAG[LRWL]=1'b1;		
		WA_BAD=BAD;			
              end
            end

            old_BANK_STAT = BANK_STAT[BAD] ;
            old_BANK_STAT[2:1] = 2'b00 ;
            BANK_STAT[BAD] = old_BANK_STAT ;

          end 
        end  

        if(MODE_REG_READ != 0) begin 
          iQ = {WIDTH_of_DATA{1'bz}} ;
          if(A[0] == 0) iQ[3:0] = {BT_REG,BL_REG[2:0]};
          else          iQ[3:0] = {OP_REG,CL_REG[2:0]};

          MODE_REG_READ = 0 ;

          
          OQ[CL_REG] = iQ ;
          OUT_FLAG[CL_REG] = 1 ;
          MRR_FLAG[CL_REG] = 1 ;
          T_CAC[CL_REG] = $time + TCAC ;
        end  

        
        if(DQMS != 0) begin
        
          for(i=0;i<WIDTH_of_DQM;i=i+1) begin
            DQE1[i] = ~ DQMS[i] ;
          end
          DQE[LDQZ] = DQE1 ; 
        end

        for(i=0;i<MAX_CL;i=i+1) begin
          BCF[i] = BCF[i + 1] ;
        end
        BCF[MAX_CL] = 0 ;

      end  

      oCLK = 1 ;  

  end  

  always @(posedge oCLK) begin :OUTPUT_BUFFER 
      
      if(HLD_CKE[0] == 0) disable OUTPUT_BUFFER ;

      for(i=0;i<MAX_CL;i=i+1) begin
        T_CAC[i]    = T_CAC[i + 1] ;
        OQ[i]       = OQ[i + 1] ;
        OUT_FLAG[i] = OUT_FLAG[i + 1] ;
        MRR_FLAG[i] = MRR_FLAG[i + 1] ;
        DQE[i]      = DQE[i + 1] ;
      end
      T_CAC[MAX_CL]    = 0 ;
      

      OUT_FLAG[MAX_CL] = 0 ;
      MRR_FLAG[MAX_CL] = 0 ;
      DQE[MAX_CL]      = {WIDTH_of_DQM{1'b1}} ;

      OUTPUT_COMPLETE = 0 ;

      begin
	fork		
	  #TOLZ begin
        	Q     = {WIDTH_of_DATA{1'bx}} ;
          	DQE0 = DQE[0] ;

		for(i=0;i<WIDTH_of_DQM;i=i+1) begin
		  for(j=i*UNIT_of_DQM;j<(i+1)*UNIT_of_DQM;j=j+1) begin




		      if(PREV_OUT_FLAG[j] == 0)
            	        OUTCTL[j] = DQE0[i] & OUT_FLAG[0] ;

		  end
       		end

	  end
          #TOH begin
		for(i=0;i<WIDTH_of_DQM;i=i+1) begin
		  for(j=i*UNIT_of_DQM;j<(i+1)*UNIT_of_DQM;j=j+1) begin
		    if(PREV_OUT_FLAG != 0)
        	      Q[j] = 1'bx ;
		  end
		end
          end
	  #(TOHZ_MAX[CL_REG]) begin
          	DQE0 = DQE[0] ;
		for(i=0;i<WIDTH_of_DQM;i=i+1) begin
		  for(j=i*UNIT_of_DQM;j<(i+1)*UNIT_of_DQM;j=j+1) begin

		    if(PREV_OUT_FLAG[j] !=0) begin
           	      OUTCTL[j] = DQE0[i] & OUT_FLAG[0] ;
end


          	  end
       		end
	  end
          #T_OVC begin
		Q_WK = OQ[0];
		for(i=0;i<WIDTH_of_DQM;i=i+1) begin
		  for(j=i*UNIT_of_DQM;j<(i+1)*UNIT_of_DQM;j=j+1) begin
           	    
			if((DQE0[i] & OUT_FLAG[0]) == 1) Q[j] = Q_WK[j] ;
          	  end
       		end

	  end
	join
      end


        if(OUTCTL != 0)  OWD_CTL[0] = 1'b1 ;
	PREV_OUT_FLAG = OUTCTL;

      OUTPUT_COMPLETE = 1 ;

  end  
always @(WARNING) begin : WARNING_MESSAGE
  $write("%t : Warning MSG from 64MSDRAM. Code=%d \n",$time,ERR_CODE) ;
  case(ERR_CODE)
    1001 : $write("             Lack of Address  Hold Time(<%0t).\n",THI);
    1002 : $write("             Lack of Data-in  Hold Time(<%0t).\n",THI) ;
    1003 : $write("             Lack of Command  Hold Time(<%0t).\n",THI ) ;
    1004 : $write("             Lack of CKE      Hold Time(<%0t).\n",THI ) ;
    1005 : $write("             Lack of DQM      Hold Time(<%0t).\n",THI ) ;
    1006 : $write("             Lack of CS       Hold Time(<%0t).\n",THC ) ;
    1007 : $write("             Lack of Clock    Low Time(<%0t)\n",TCL) ;
    1008 : $write("             Lack of Address Setup Time(<%0t).\n",TSI) ;
    1009 : $write("             Lack of Data-in Setup Time(<%0t).\n",TSI) ;
    1010 : $write("             Lack of Command Setup Time(<%0t).\n",TSI ) ;
    1011 : $write("             Lack of CKE     Setup Time(<%0t).\n",TSI ) ;
    1012 : $write("             Lack of DQM     Setup Time(<%0t).\n",TSI ) ;
    1013 : $write("             Lack of CS      Setup Time(<%0t).\n",TSC ) ;
    1014 : $write("             Lack of Clock High Time(<%0t)\n",TCH) ;
    endcase
    ERR_CODE=0;
end
  always @(ILLEGAL) begin : ILLEGAL_OPERATION_with_MESSAGE
    $write("%t : Illegal Operation.\n",$time) ;
    case(ERR_CODE)
    3001 : $write("             Illegal operation in Auto-precharge or internal precharge state.\n");
    3002 : $write("             Invalid mode. A7=1\n");
    3003 : $write("             Invalid mode. A8=1\n");
    3004 : $write("             Invalid mode.\n");
    3005 : $write("             Bank is not Idle state.\n");
    3006 : $write("             Select bank is Idle state.\n");
    3007 : $write("             READA or WRITA is inturrupted by WRITE.\n");
    3008 : $write("             Illegal command in READA state.\n");
    3009 : $write("             Bank is Idle state.\n");
    3010 : $write("             Any banks are READA or WRITA state.\n");
    3011 : $write("             Illega command in READA state.\n");
    3012 : $write("             Does not support FULL BURST MODE.\n");
    3013 : $write("             Attempt to set MRS command in Non-Idle state.\n");
    3014 : $write("             Attempt to use REFR command in Non-Idle state.\n");
    endcase
    ERR_CODE=0;

    case(ERROR_STOP)
      0: ;
      1: $stop;
      default:$finish;
    endcase
  end

  always @(ILLEGAL_TIMING) begin : TIMING_ERROR
  
  $write("%t : Illegal timing MSG from 64MSDRAM. Code=%d \n",$time,ERR_CODE) ;
    case(ERR_CODE)
    1501 : $write("             Dangerous Operation in exiting Power down state. Recommend NOP/DESL.\n");
    1502 : $write("             Over tREF. PD enter %t\n",T_PD_ENTER) ;
    1503 : $write("             Illegal Operation in exiting SREF state. Only NOP/DESL is enable.\n");
    1504 : $write("             Exiting SREF state by illegal Operation. Only NOP/DESL is enable.\n");
    1505 : $write("             tCLK is too short(< %t)\n",TCLK[CL_REG]);
    1506 : $write("             Over tRAS. BANK %0d\n",ERR_PARM);
    1507 : $write("             Lack of tRC.\n");
    1508 : $write("             Lack of tRRD.\n");

    1509 : $write("             Lack of lRWL\n");		
    1510 : $write("             Lack of tRRD.\n");
    1511 : $write("             Lack of lOWD.\n") ;
    1512 : $write("             Lack of tRCD(<%0t). Bank Activate at %0t\n",TRCD,T_BANK_ACTIVE[BS]);
    1513 : $write("             Lack of tWR.\n");
    1514 : $write("             Lack of tRCD(<%0t). Bank Activate at %0t\n",TRCD,T_BANK_ACTIVE[BS]);
    1515 : $write("             Lack of tRAS.\n");
    endcase
    ERR_CODE=0;
    case(ERROR_STOP)
      0: ;
      1: $stop;
      default:$finish;
    endcase
  end

  always @(ILLEGAL_CKE) begin : ILLEGAL_CKE_FALL
  
  $write("%t : Illegal CKE timing MSG from 64MSDRAM. Code=%d \n",$time,ERR_CODE) ;
    case(ERR_CODE)
    2001 : $write("             Illegal CKE fall edge before lapse of lMRD.\n");
    2002 : $write("             Illegal CKE fall edge in Auto-Refresh state.\n");
    2003 : $write("             Illegal CKE fall edge between WRITA Burst-End and Precharge-Start\n");
    2004 : $write("             Illegal CKE fall edge in WRITA burst end.\n");
    2005 : $write("             Illegal CKE fall edge.\n");
    endcase

    case(ERROR_STOP)
      0: ;
      1: $stop;
      default:$finish;
    endcase
  end
  always @(ILLEGAL_OPE) begin : ILLEGAL_OPERATION
  
  $write("%t : Illegal Operation MSG from 64MSDRAM. Code=%d \n",$time,ERR_CODE) ;
    case(ERR_CODE)
    2501 : $write("             Illegal operation before lapse of lMRD\n");
    2502 : $write("             Illegal operation in Self Refresh Recovery.\n");
    2503 : $write("             Illegal operation in Self Refresh Recovery.\n");
    2504 : $write("             Illegal operation in Auto Refresh state.\n");
    2505 : $write("             BL_REG=%b. Invalid Value.\n",A[2:0]);
    2506 : $write("             CL_REG = %b. Invalid Value.\n",A[6:4]);
    2509 : $write("             Illegal operation(BSTP) in precharging state.\n");
    endcase
    ERR_CODE=0;
    case(ERROR_STOP)
      0: ;
      1: $stop;
      default:$finish;
    endcase
  end




  always @( A ) begin
    T_TRAN_ADD = $time ;

    if( (T_CLK_FALL != T_CLK_RISE) && (T_CLK_RISE + THI > $time) ) begin
      ERR_CODE=1001;
      -> WARNING ;
      
    end
  end
  always @( D ) begin
    if( OUTCTL == 0) T_TRAN_DIN = $time ;

    if( (T_CLK_FALL != T_CLK_RISE) && (T_CLK_RISE + THI > $time) ) begin
	if(OWD_CTL == 0) begin		
      	  ERR_CODE=1002;
      	  ->WARNING ;
      
        end
    end
  end
  always @( RAS or CAS or WE ) begin
    T_TRAN_CMD = $time ;

    if( (T_CLK_FALL != T_CLK_RISE) && (T_CLK_RISE + THI  > $time) ) begin
      ERR_CODE=1003;
      ->WARNING;
      
    end
  end
  always @( CKE ) begin
    T_TRAN_CKE = $time ;

    if( (T_CLK_FALL != T_CLK_RISE) && (T_CLK_RISE + THI  > $time) ) begin
      ERR_CODE=1004;
      ->WARNING ;
      
    end
  end
  always @( DQMS ) begin
    T_TRAN_DQM = $time ;

    if( (T_CLK_FALL != T_CLK_RISE) && (T_CLK_RISE + THI  > $time) ) begin
      ERR_CODE=1005;
      ->WARNING;
      
    end
  end
  always @( CS ) begin
    T_TRAN_CSL = $time ;

    if( (T_CLK_FALL != T_CLK_RISE) && (T_CLK_RISE + THC  > $time) ) begin
      ERR_CODE=1006;
      ->WARNING;
      
    end
  end


  task PRECHG_SET;
    output [63:0] T_PCHG_OUT ;
    inout  [4:0] BANK_STAT ;
    input  [63:0] T_BANK_ACTIVE ;
    begin
      if(BANK_STAT[2] == 1'b1) begin 
        if((T_BANK_ACTIVE + TRAS_MIN) > ($time + TRWL)) begin
          
            ERR_CODE=1515;
	    -> ILLEGAL_TIMING ;  
          BANK_STAT = 4'b0001 ;
        end
        else begin
          T_PCHG_OUT = ($time + TRP) + TRWL ;
          BANK_STAT = 4'b1000 ;
        end
      end  
      else begin  
        if((T_BANK_ACTIVE + TRAS_MIN) > $time) begin
          
          ERR_CODE=1515;
          -> ILLEGAL_TIMING ;  
          BANK_STAT = 4'b0001 ;
        end
        else begin
          T_PCHG_OUT = $time + TRP ;
          BANK_STAT = 4'b1000 ;
        end
      end  
    end
  endtask  



task READ_MEM ;
   input [WIDTH_of_BAD-1:0] bank ; 
   input [ WIDTH_of_RAD-1:0] row ; 
   input [7:0]  col ;
  output [15:0] databus ;
  reg [15:0] databus ;

  databus = mem[{bank,row,col}] ;
endtask

task WRITE_MEM ;
   input [WIDTH_of_BAD-1:0] bank ; 
   input [ WIDTH_of_RAD-1:0] row ; 
   input [7:0]  col ;
  input [15:0] databus ;

  mem[{bank,row,col}] = databus ;
endtask
endmodule

`endprotect

`endcelldefine