/*
$Id: verilogmodule.cpp,v 1.29 2002/04/17 13:51:53 dirkl Exp $
$Log: verilogmodule.cpp,v $
Revision 1.29  2002/04/17 13:51:53  dirkl
- added delay #100 to register-assignments (for simulation only)

Revision 1.28  2002/03/27 21:10:10  dirkl
*** empty log message ***

Revision 1.27  2002/03/27 19:58:39  dirkl
*** empty log message ***

Revision 1.26  2002/03/24 12:19:14  dirkl
- now it really works

Revision 1.25  2002/03/23 18:38:33  dirkl
*** empty log message ***

Revision 1.24  2002/03/21 16:55:51  dirkl
- support for multiple connect_outside functions seems to work

Revision 1.23  2002/03/04 09:53:21  dirkl
*** empty log message ***

Revision 1.22  2002/02/25 23:34:15  dirkl
- connections of bus_protocol get now connected to the top-level module(very uggly implementation)

Revision 1.21  2001/10/25 16:39:02  dirkl
- new line for each parameter ==> no more "line too long"-error in VerilogXL

Revision 1.20  2001/06/12 11:38:44  dirkl
- extended support for predefined function:s

Revision 1.19  2001/06/12 11:05:45  sbeyer
* added clk propagation to all modules

Revision 1.18  2001/05/31 14:20:40  sbeyer
* completed support for arrays
* fixed constant support

Revision 1.17  2001/05/30 18:07:59  sbeyer
* added array and ram support in types
* BETA support for function lookup table

Revision 1.16  2001/05/17 12:12:20  dirkl
- added command-line option --no-translation

Revision 1.15  2001/03/17 11:21:03  sbeyer

added short names for module instances (XILINX restricts names to 500 characters)

Revision 1.14  2001/03/14 11:13:11  sbeyer

all signal names now end with 'x' (no longer with a number)

Revision 1.13  2001/02/05 13:44:09  sbeyer

fixed bug in register support

Revision 1.12  2001/02/05 11:14:46  sbeyer

added register support

Revision 1.11  2001/01/26 15:11:18  sbeyer

added cvs log

*/
#include "verilogmodule.h"
#include "synthesize_core.h"

VerilogModule::VerilogModule(const string &modulename,
                             const type_array &_register_type/*=type_array()*/)
{
  parameteranzahl=outside_parameteranzahl=module_count=wire_count=internal_wire_count=0;

  register_type=_register_type;
  register_declared=false;
  anfang=newstringlist("module ");
  stringlist_append(anfang,modulename.c_str());
  name=modulename;
  parameter=stringlist_append(anfang,"(");
  outside_connection_parameter=stringlist_append(anfang," ");
  input_output=stringlist_append(anfang,");\n");
  wires=stringlist_append(anfang,"\n");
  assigns=stringlist_append(anfang,"\n");
  register_assigns=stringlist_append(anfang,"\n");
  moduleaufrufe=stringlist_append(anfang,"\n");
  stringlist_append(anfang,"\nendmodule\n");
  // add clk parameter to every module
  parameter=stringlist_einfuegen(parameter,"clk");
  parameter_str="clk";
  input_output=stringlist_einfuegen(input_output,"\tinput clk;\n");
}

VerilogModule::~VerilogModule()
{
  stringlist_freigeben(anfang);
}

void VerilogModule::reset_outside_parameteranzahl()
{
  outside_parameteranzahl=0;
}

void VerilogModule::new_wiredefinition(int bitbreite,
                                       const string &name,
                                       bool is_default_name/*=false*/)
{
  char merke[11]; // !!! bitbreite hat hoechstens 5 Stellen
  wires=stringlist_einfuegen(wires,"\twire ");
  if (bitbreite>1)
    {
      sprintf(merke,"[%d:0] ",bitbreite-1);
      wires=stringlist_einfuegen(wires,merke);
    }
  sprintf(merke,"wire%ix",internal_wire_count++);
  translation_tab.push_front(wire_translator(name,merke));
  wires=stringlist_einfuegen(wires,merke);
  wires=stringlist_einfuegen(wires,";");
  if (parameter_hdl_comment && !is_default_name)
    wires=stringlist_einfuegen(wires,("\t// external name: "+name).c_str());
  wires=stringlist_einfuegen(wires,"\n");
}

void VerilogModule::new_inputparameter(int bitbreite,const string &name)
{
  char merke[10],tmp[10]; // !!! bitbreite hat hoechstens 5 Stellen

  // parameter deklarieren
  parameter=stringlist_einfuegen(parameter,",\n\t\t");

  sprintf(tmp,"a_%ix",parameteranzahl);
  translation_tab.push_front(wire_translator(name,tmp));
  parameteranzahl++;
  parameter=stringlist_einfuegen(parameter,tmp);

  // parameter_string 
  parameter_str+=",\n\t\t"+string(tmp);

  // Typ des Parameters angeben
  input_output=stringlist_einfuegen(input_output,"\tinput ");
  if (bitbreite>1)
    {
      sprintf(merke,"[%d:0] ",bitbreite-1);
      input_output=stringlist_einfuegen(input_output,merke);
    }
  input_output=stringlist_einfuegen(input_output,tmp);
  input_output=stringlist_einfuegen(input_output,";");
  if (parameter_hdl_comment)
    input_output=stringlist_einfuegen(input_output,("\t// external name: "+name).c_str());
  input_output=stringlist_einfuegen(input_output,"\n");
}


string VerilogModule::new_outside_inputparameter(int bitbreite,const string &name,bool first,string functionname)
{
  char merke[10],tmp[512], tmp2[10]; // !!! bitbreite hat hoechstens 5 Stellen
  string returns="";

  // parameter deklarieren

  outside_connection_parameter=stringlist_einfuegen(outside_connection_parameter,",\n\t\t");

  sprintf(tmp,("bp_" + functionname + "_a%ix").c_str(),outside_parameteranzahl);
  sprintf(tmp2,"a_%ix",outside_parameteranzahl);
  returns=string(tmp);
  translation_tab.push_front(wire_translator(name,tmp));
  outside_parameteranzahl++;
  outside_connection_parameter=stringlist_einfuegen(outside_connection_parameter,tmp);

  // parameter_string 
  parameter_str+=",\n\t\t"+string(tmp);

  // Typ des Parameters angeben
  input_output=stringlist_einfuegen(input_output,"\toutput ");
  if (bitbreite>1)
    {
      sprintf(merke,"[%d:0] ",bitbreite-1);
      input_output=stringlist_einfuegen(input_output,merke);
    }
  input_output=stringlist_einfuegen(input_output,tmp);
  input_output=stringlist_einfuegen(input_output,";");
  if (parameter_hdl_comment)
    input_output=stringlist_einfuegen(input_output,"\t// connection to TOP-Level Modul: ");
  input_output=stringlist_einfuegen(input_output,"\n");

  // falls first=true wird noch ein assign eingefügt
  if (first)
    {
      this->new_assign(string(tmp),string(tmp2),false);
    }

  return returns;
}

void VerilogModule::new_outputparameter(int bitbreite,const string &name)
{
   char merke[10],tmp[10]; // !!! bitbreite hat hoechstens 5 Stellen

  // parameter deklarieren

  parameter=stringlist_einfuegen(parameter,",\n\t\t");
  sprintf(tmp,"out_%ix",parameteranzahl);
  translation_tab.push_front(wire_translator(name,tmp));
  parameteranzahl++;
  parameter=stringlist_einfuegen(parameter,tmp);

  // parameter_string 
  parameter_str+=",\n\t\t"+string(tmp);
  
  // Typ des Parameters angeben
  input_output=stringlist_einfuegen(input_output,"\toutput ");
  if (bitbreite>1)
    {
      sprintf(merke,"[%d:0] ",bitbreite-1);
      input_output=stringlist_einfuegen(input_output,merke);
    }
  input_output=stringlist_einfuegen(input_output,tmp);
  input_output=stringlist_einfuegen(input_output,";");
  if (parameter_hdl_comment)
    input_output=stringlist_einfuegen(input_output,("\t// external name: "+name).c_str());
  input_output=stringlist_einfuegen(input_output,"\n");
}

string VerilogModule::new_outside_outputparameter(int bitbreite,const string &name,bool first,string functionname)
{
  char merke[10],tmp[512], tmp2[10]; // !!! bitbreite hat hoechstens 5 Stellen
  string returns="";

  // parameter deklarieren

  outside_connection_parameter=stringlist_einfuegen(outside_connection_parameter,",\n\t\t");
  sprintf(tmp,("bp_" + functionname + "_out%ix").c_str(),outside_parameteranzahl);
  returns=string(tmp);
  sprintf(tmp2,"out_%ix",outside_parameteranzahl);
  translation_tab.push_front(wire_translator(name,tmp));
  outside_parameteranzahl++;
  outside_connection_parameter=stringlist_einfuegen(outside_connection_parameter,tmp);

  // parameter_string 
  parameter_str+=",\n\t\t"+string(tmp);
  
  // Typ des Parameters angeben
  input_output=stringlist_einfuegen(input_output,"\tinput ");
  if (bitbreite>1)
    {
      sprintf(merke,"[%d:0] ",bitbreite-1);
      input_output=stringlist_einfuegen(input_output,merke);
    }
  input_output=stringlist_einfuegen(input_output,tmp);
  input_output=stringlist_einfuegen(input_output,";");
  if (parameter_hdl_comment)
    input_output=stringlist_einfuegen(input_output,"\t// connection to TOP-Level Modul:");
  input_output=stringlist_einfuegen(input_output,"\n");

  // falls first=true wird noch ein assign eingefügt
  if (first)
    {
      this->new_assign(string(tmp2),string(tmp),false);
    }

  return returns;
}

void VerilogModule::new_register(int bitbreite,const string &name, int index)
{
  char merke[10]; // !!! bitbreite hat hoechstens 5 Stellen

  wires=stringlist_einfuegen(wires,"\treg  ");
  if (bitbreite>1)
    {
      sprintf(merke,"[%d:0] ",bitbreite-1);
      wires=stringlist_einfuegen(wires,merke);
    }
  sprintf(merke,"reg_%ix",index);
  translation_tab.push_front(wire_translator(name,merke));
  wires=stringlist_einfuegen(wires,merke);
  wires=stringlist_einfuegen(wires,";");
  if (parameter_hdl_comment)
    wires=stringlist_einfuegen(wires,("\t// external name: "+name).c_str());
  wires=stringlist_einfuegen(wires,"\n");
}

string VerilogModule::new_wiredefinition(const type_array &tarray)
{
  char name[16];
  snprintf(name,16,"wire%i`",wire_count++);
  for (int i=0;i<tarray.num;i++)
    if (tarray.type[i]!=ram)
      new_wiredefinition(tarray.bitbreite[i],name+tarray.name[i],true);
  return name;
}

string VerilogModule::new_wiredefinition(int width)
{
  char name[16];
  snprintf(name,16,"wire%i`",wire_count++);
  new_wiredefinition(width,name,true);
  return name;
}

void VerilogModule::new_wiredefinition(const string &name, 
                                       const type_array &tarray)
{
  for (int i=0;i<tarray.num;i++)
    if (tarray.type[i]!=ram)
      new_wiredefinition(tarray.bitbreite[i],name+tarray.name[i]);
}

void VerilogModule::new_inputparameter(const var &param)
{
  int reg_start=0, reg_end=0;
  if (!register_declared && register_type.num)
    if (param.tarray.is_member(register_type,reg_start,reg_end))
    {
      register_declared=true;
      register_assigns=stringlist_einfuegen(register_assigns,
             "\talways @ (posedge clk)\n\tbegin\n");
      stringlist_einfuegen(register_assigns,"\tend\n");
    }
  for (int i=0;i<param.tarray.num;i++)
    if (param.tarray.type[i]!=ram)
      if (i>=reg_start && i<reg_end)
        new_register(param.tarray.bitbreite[i],param.name + param.tarray.name[i],i-reg_start);
      else
        new_inputparameter(param.tarray.bitbreite[i],param.name + param.tarray.name[i]);
}

// als rueckgabe gibt es einen string, mit den feedthrough-parametern
string VerilogModule::new_outside_inputparameter(const var &param,bool first,string functionname)
{
  int reg_start=0, reg_end=0;
  string returns="";
  for (int i=0;i<param.tarray.num;i++)
    if (param.tarray.type[i]!=ram)
      returns+=',' + new_outside_inputparameter(param.tarray.bitbreite[i],param.name + param.tarray.name[i],first,functionname);

  return returns;
}

string VerilogModule::new_outputparameter(const type_array &tarray)
{
  int reg_start=0, reg_end=0;
  if (register_declared && register_type.num)
    if (!tarray.is_member(register_type,reg_start,reg_end))
      raise_error(cout << "register type expected in function output\n");
  string name="out`";
  for (int i=0;i<tarray.num;i++)
    if (tarray.type[i]!=ram)
      if (i>=reg_start && i<reg_end)
      {
        char tmp[16]; // define 'alias' for register name
        snprintf(tmp,16,"reg_%ix",i-reg_start);
        translation_tab.push_front(wire_translator(name + tarray.name[i],tmp));
      }
      else
        new_outputparameter(tarray.bitbreite[i],name + tarray.name[i]);
  return name;
}

string VerilogModule::new_outside_outputparameter(const type_array &tarray,bool first,string functionname)
{
  int reg_start=0, reg_end=0;
  string returns="";

  for (int i=0;i<tarray.num;i++)
    if (tarray.type[i]!=ram)
      returns+=',' + new_outside_outputparameter(tarray.bitbreite[i],name + tarray.name[i],first,functionname);

  return returns;
}

string VerilogModule::wire_function_call(const string &wire, 
                                         const type_array &tarray) const
{
  string ret;
  for (int i=0;i<tarray.num;i++)
    if (tarray.type[i]!=ram)
      ret += (ret.empty()? wire_name(wire + tarray.name[i]) : 
                        ",\n\t\t" + wire_name(wire + tarray.name[i]));
  return ret;
}

string VerilogModule::wire_name(const string &wire) const
{
  if (parameter_no_translation)
    {
      return wire;
    }
  else
    {
      list<wire_translator>::const_iterator i=translation_tab.begin();
      while (i!= translation_tab.end())
        {
          if (i->pvs_name==wire)
            return i->hdl_name;
          i++;
        }
      raise_error(cout << "internal error: pvs wire name " << wire << " not declared!\n");
    }
}

list<string> VerilogModule::wire_names(const string &wire, 
                                       const type_array &tarray) const
{
  list<string> ret;
  for (int i=0;i<tarray.num;i++)
    if (tarray.type[i]!=ram)
      ret.push_back(wire_name(wire+tarray.name[i]));
    else
      ret.push_back("internal error");
  return ret;
}

bool VerilogModule::is_simple_wire_name(const string &name) const
{
  list<wire_translator>::const_iterator i=translation_tab.begin();
  while (i!= translation_tab.end())
  {
    if (i->hdl_name==name)
      return true;
    i++;
  }
  return false;
}

void VerilogModule::free_local_wire_names(int num)
{
  for (int i=0;i<num;i++)
    translation_tab.pop_front();
}

void VerilogModule::new_moduleaufruf(const string &modulename,const string &parameter,const string feedthrough_parameter)
{
  char temp[10]; // !!! instanznummer darf hoechstens 10 Stellen haben

  moduleaufrufe=stringlist_einfuegen(moduleaufrufe,"\t");
  moduleaufrufe=stringlist_einfuegen(moduleaufrufe,modulename.c_str());
  moduleaufrufe=stringlist_einfuegen(moduleaufrufe," ");
  // short instanze name
  sprintf(temp,"m%d",module_count++);
  moduleaufrufe=stringlist_einfuegen(moduleaufrufe,temp);
  if (parameter.size())
    {
      moduleaufrufe=stringlist_einfuegen(moduleaufrufe," (");
      moduleaufrufe=stringlist_einfuegen(moduleaufrufe,parameter.c_str());
      // falls es sich um eine feedthrough-Funktion handelt, noch die passenden Parameter einfuegen
      moduleaufrufe=stringlist_einfuegen(moduleaufrufe,feedthrough_parameter.c_str());
      moduleaufrufe=stringlist_einfuegen(moduleaufrufe,")");
    }
  moduleaufrufe=stringlist_einfuegen(moduleaufrufe,";\n");
}

void VerilogModule::new_assign(const string &leftside,const string &rightside,bool lookup)
{
  string name;
  if (lookup)
    {
      name=wire_name(leftside);
    }
  else
    {
      name=leftside;
    }
  if (name.find("reg_")==0) // register assign?
  {
    register_assigns=stringlist_einfuegen(register_assigns,"\t\t");
    register_assigns=stringlist_einfuegen(register_assigns,name.c_str());
    register_assigns=stringlist_einfuegen(register_assigns," <= #100 ");
    register_assigns=stringlist_einfuegen(register_assigns,rightside.c_str());
    register_assigns=stringlist_einfuegen(register_assigns,";\n");
  }
  else
  {
    assigns=stringlist_einfuegen(assigns,"\tassign ");
    assigns=stringlist_einfuegen(assigns,name.c_str());
    assigns=stringlist_einfuegen(assigns," = ");
    assigns=stringlist_einfuegen(assigns,rightside.c_str());
    assigns=stringlist_einfuegen(assigns,";\n");
  }
}

void VerilogModule::new_assign(const string &leftside,const string &rightside,const type_array &tarray)
{
  for (int i=0;i<tarray.num;i++)
    if (tarray.type[i]!=ram)
      {
	new_assign(leftside+tarray.name[i],rightside+tarray.name[i]);
      }
    else
     ; //ram-assignment
}

void VerilogModule::new_assign(const string &leftside,const list<string> &rightside,const type_array &tarray)
{
  list<string>::const_iterator j=rightside.begin();
  for (int i=0;i<tarray.num;i++,j++)
    if (tarray.type[i]!=ram)
      {
	new_assign(leftside+tarray.name[i],*j);
      }
    else
     ; //ram-assignment
}

struct stringlisten_eintrag *VerilogModule::getanfang() const
{
  return anfang;
}

ostream &operator<<(ostream& ausgabe, const VerilogModule& module)
{
  struct stringlisten_eintrag *temp;

  temp=module.getanfang();
  while (temp)
    {
      ausgabe << temp->text;
      temp=temp->next;
    }
  
  return ausgabe << endl; // append extra newline
}