/*
$Id: synthesize_core.h,v 1.8 2002/12/02 14:36:58 sbeyer Exp $
$Log: synthesize_core.h,v $
Revision 1.8  2002/12/02 14:36:58  sbeyer
* ported source to gcc-3.2 (still compiles AND WORKS with gcc-2.9x)

Revision 1.7  2002/03/21 13:54:54  dirkl
*** empty log message ***

Revision 1.6  2002/02/25 23:34:15  dirkl
- connections of bus_protocol get now connected to the top-level module(very uggly implementation)

Revision 1.5  2001/05/30 18:07:58  sbeyer
* added array and ram support in types
* BETA support for function lookup table

Revision 1.4  2001/01/26 16:23:17  sbeyer

fixed record bugs, fill bug;
proper record treatment in synthesize_simple_expression made postfix obsolete;
removed a few obsolete 'wire1=wire2' - assignments
started (or rather tried to start) record support for 'if' and 'cond' (a little tricky)

Revision 1.3  2001/01/22 18:14:12  sbeyer

implemented wire translation and hdl-comments

Revision 1.2  2001/01/21 17:25:29  sbeyer

improved record support considerably; added 'LET x=const' simplification

Revision 1.1  2001/01/18 16:09:32  sbeyer

too many changes to mention; a 16-bit-carry-chain-adder can now be synthesized

*/
#ifndef synthesize_core_h
#define synthesize_core_h

#include "synthesize.h"
#include "synthesize_type.h"
#include "shared_lists.h"
#include "verilogmodule.h"
#include <fstream>

using namespace std;

#define fun_error(COUT,fun) { COUT; cout << "synthesize failed for function " << fun.name << " in file " << fun.root->source_file << ", line " << fun.root->source_line; exit(1); }

// the record dereferencing operator
#define REC_DEREF '`'

// the file stream for the output
extern ofstream ostr;

// helper
bool is_constant(const knoten *const root, int& value);

// holds info-strings about pvs-files
extern string pvs_fileinfo;

// var stores types and names of local variables in a function
// (either from parameters or non-const LETs
struct var
{
  string     name;
  type_array tarray;

  var(){ }

  var(const var& x)
    { name=x.name; tarray=x.tarray; }

  var(const string &_name, const type_array &_tarray)
    { name=_name; tarray=_tarray; }

  friend ostream &operator << (ostream& ostr, const var &x);
};

bool is_var_defined(const list<var>  &vars, 
                    const string     &name,
					      type_array &tarray);

struct synthesized_function
{
  string name;
  string bindings;
  list<var> parameters;
  type_array return_type;

  synthesized_function(){ }

  synthesized_function(const synthesized_function &synth);

  synthesized_function(const string &_name, const string &_bindings)
    { name=_name; bindings=_bindings; }

  friend ostream &operator << (ostream& ostr, const
			       synthesized_function &function);
};

extern list<synthesized_function> synthesized_functions;

bool is_function_in_lookup_table(const string &_name);

string compose_record_name(const string &prefix, const string &name);
string inv_compose_record_name(const string &name, const string &postfix);

bool is_function_synthesized(const string &_name, 
                             const string &_bindings,
                             synthesized_function &function);

string binding_string(const list<binding> &bindings);

string synthesize_function_call(const knoten        *const root,
                                const list<var>     &vars,
                                      VerilogModule &module,
                                      type_array    &tarray,
                                      bool          &translated);

// 'prefix'  : accumulated prefix from record assignment (# #)
// 'postfix' : accumulated postfix from record dereferencing `
list<string> synthesize_record_expression(const knoten        *const copy, 
                                                type_array    &tarray, 
                                                VerilogModule &module,
                                          const list<var>     &vars,
                                          const string        &postfix);

string synthesize_simple_expression(const knoten        *const root, 
                                          VerilogModule &module,
                                    const list<var>     &vars,
                                          int           &width);

// synthesize_function synthesizes 'function' with 'bindings'
// assumes that all actuals are bound
synthesized_function synthesize_function(const defined_function &function, 
                                         const list<binding>    &bindings,
					 const string           parentname,
                                         bool                    raise_error=true);

#endif // synthesize_core_h