Institute for Computer Architecture
and Parallel Computing
System Architecture: An Ordinary Engineering Discipline
Cover Wolfgang J. Paul, Christoph Baumann, Petro Lutsyk, Sabine Schmaltz

The pillars of the bridge on the cover of this book date from the Roman Empire and they are in daily use today, an example of conventional engineering at its best. Modern commodity operating systems are examples of current system programming at its best, with bugs discovered and fixed on a weekly or monthly basis. This book addresses the question of whether it is possible to construct computer systems that are as stable as Roman designs.

The authors successively introduce and explain specifications, constructions and correctness proofs of a simple MIPS processor; a simple compiler for a C dialect; an extension of the compiler handling C with inline assembly, interrupts and devices; and the virtualization layer of a small operating system kernel. A theme of the book is presenting system architecture design as a formal discipline, and in keeping with this the authors rely on mathematics for conciseness and precision of arguments to an extent common in other engineering fields.

This textbook is based on the authors' teaching and practical experience, and it is appropriate for undergraduate students of electronics engineering and computer science. All chapters are supported with exercises and examples.

Published by Springer, 2016 | ISBN: 978-3-319-43065-2
A Pipelined Multi-core MIPS Machine - Hardware Implementation and Correctness Proof
Cover Mikhail Kovalev, Silvia M. Mueller, Wolfgang J. Paul

Content: This monograph is based on the third author's lectures on computer architecture, given in the summer semester 2013 at Saarland University, Germany. It contains a gate level construction of a multi-core machine with pipelined MIPS processor cores and a sequentially consistent shared memory.

The book contains the first correctness proofs for both the gate level implementation of a multi-core processor and also of a cache based sequentially consistent shared memory. This opens the way to the formal verification of synthesizable hardware for multi-core processors in the future.

Constructions are in a gate level hardware model and thus deterministic. In contrast the reference models against which correctness is shown are nondeterministic. The development of the additional machinery for these proofs and the correctness proof of the shared memory at the gate level are the main technical contributions of this work.

Errata | Published by Springer, 2014 | ISBN: 978-3-319-13905-0
Computer Architecture: Complexity and Correctness
Cover Silvia M. Mueller, Wolfgang J. Paul

Computer Architecure: Complexity and Correctness develops, at the gate level, the complete design of a pipelined RISC processor with delayed branch, forwarding, hardware interlock, precise maskable nested interrupts, caches, and a fully IEEE-compliant floating point unit.

In contrast to other design approaches applied in practice and unlike other textbooks available, the designs presented here are modular, clean and complete up to the construction of entire complex machines. The authors' systematically basing their approach on rigorous mathematical formalisms allows for rigorous correctness proofs, accurate hardware cost determination, and performance evaluation as well as, generally speaking, for coverage of a broad variety of relevant issues within a reasonable number of pages.

The book is written as a text for classes on computer architecture and related topics and will serve as a valuable source of reference for professionals in hardware design. The presentation is completely self-contained. Numerous illustrations, examples, exercises, and a subject index suppert the reader in accessing the material presented.

Errata | Published by Springer, 2000 | ISBN: 3-540-67481-0
The Complexity of Simple Computer Architectures
Cover Silvia M. Mueller, Wolfgang J. Paul

This book presents a formal model for evaluating the cost effectiveness of computer architectures, from CPU design to parallel supercomputers.

Techincally speaking, the authors exhibit an easy way to interprete architectures presented in modern textbooks as complete designs and to derive their cost and cycle time. To illustrate the formal procedure of trade-off analyses, several non-pipelined design alternatives for the well known RISC architecture called DLX are analyzed quantitatively. Among other thinds, the cost and run time impact of full hardware support for precise interrupts are determined and a comparison of hardwired and mircocoded control is performed. Furthermore, it is formally proved that the interrupt mechanism proposed for the DLX architecture handles nested interrupts correctly.

In a detailed appendix all programs required to compute the cost and cycle time of the design described are listed in C code. A PC on which to run these simple C programs is all one needs to verify the results presented. This book addresses design professionals as well as students in computer architecture.

Published by Springer, 1995 | ISBN: 3-540-60580-0
Hardware Design: Formaler Entwurf digitaler Schaltungen
Cover Jörg Keller, Wolfgang J. Paul

"Das vorliegende Lehrbuch beschäftigt sich in mathematisch präziser Weise mit einem ganz und gar praktischen Thema, nämlich dem Entwurf von Hardware. Kapitel 1 enthält eine Diskussion mathematischer Grundbegriffe. In den Kapiteln 2 bis 4 werden die notwendigen theoretischen Grundlagen über Boole'sche Ausdrücke, Schaltkreiskomplexität und Rechnerarithmetik behandelt. Der Übergang von der abstrakten Schaltkreistheorie zum Entwurf konkreter Schaltungen findet nahtlos in Kapitel 5 statt, wo aus den Verzögerungszeiten von Gattern das zeitliche Verhalten von Flipflops und anderen Speicherbausteinen abgeleitet wird. Kapitel 6 enthält dann das vollständige Design eines einfachen Rechners.

Das Lehrbuch ist aus Vorlesungen des zweiten Autors entstanden. Kapitel 2 bis 6 enthalten den Stoff für eine einsemestrige Anfängervorlesung. Kapitel 1 ist mehr ein Nachschlagewerk für nagende Fragen, die sich früher oder später einstellen. Kapitel und Abschnitte, die mit einem Stern gekennzeichnet sind, kann man überspringen. Die Darstellung großer Teile der Kapitel 1, 5 und 6 ist neu. Die Kapitel 2 bis 4 haben einen erheblichen Anteil an fortgeschrittenem Material. Es hat sich jedoch gezeigt, daß Erstsemester damit keine besonderen Schwierigkeiten haben.

Im Einzelnen enthält Kapitel 1 eine Entwicklung des formalen Mengenkonzepts in einer für Studienanfänger verständlichen Form. Die Sätze und Beweise in diesem Kapitel sind von vorne bis hinten klassische Mathematik. Der Standpunkt, von dem aus wir sie interpretieren, ist bewußt übermütig und nicht klassisch. Wir wollen damit den Studierenden schmackhaft machen, von Zeit zu Zeit auch Wohlvertrautes von einem frischen - natürlich nicht unsinnigen - Standpunkt aus zu betrachten. Das ist insbesondere beim Forschen manchmal sehr nützlich." - aus dem Vorwort von Hardware Design: Formaler Entwurf digitaler Schaltungen, S.6

Published by B. G. Teubner Verlagsgesellschaft, 1995 | ISBN: 3-8154-2065-2
Cover Wolfgang J. Paul

Published by B. G. Teubner Verlagsgesellschaft, 1978