ALU ( lecture of 21.10.2004 )
Instruction Set Architecture (ISA) (modified on 01.12.2004)
Ph.D. Th. D.Kroening. Chapter 4: Pipelined Machines
Cache Accesses
Iakov Dalinger, Mark Hillebrand, and Wolfgang J. Paul. On the Verification of Memory Management Mechanisms. Technical Report, 2005.
Addition to the lecture of 01.02.05 (Memory Managment)
D. Kroening, S. Mueller, W. Paul, "A Rigorous Correctness Proof of a Tomasulo Scheduler Supporting Precise Interrupts"
Ph.D. Th. D.Kroening. Chapter 6: Out Of Oder Execution