module ll_logic(clk, reset, left, right, divide, leds);
	input clk, reset, left, right, divide;
	output [7:0] leds;
	reg [7:0] leds;
	
	reg [24:0] div_ctr;
	reg enable;
	
	always @(posedge clk or posedge reset)
		if (reset) begin
			div_ctr=24'h0;
			enable=0;
		end
		else if (divide) begin
				div_ctr=div_ctr-1;
				if (div_ctr==0)
					enable=1;
				else
					enable=0;
		end
		else
			enable=!enable;	
		
	always @(posedge enable or posedge reset)
		if (reset)
			leds=1;
		else
			if (left)
				leds=leds[7]?1:leds<<1;
			else if (right)
				leds=leds[0]?8'h80:leds>>1;

endmodule